[LLVMbugs] [Bug 448] NEW: [asmwritergen] Factor common instruction patterns

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.cs.uiuc.edu/bugs/show_bug.cgi?id=448

           Summary: [asmwritergen] Factor common instruction patterns
           Product: libraries
           Version: 1.3
          Platform: All
        OS/Version: All
            Status: NEW
          Severity: enhancement
          Priority: P2
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: sabre at nondot.org


The asmwriter generator currently generates a very straight-forward switch
statement to print out the instructions for a target, something like this:

bool PowerPCAsmPrinter::printInstruction(const MachineInstr *MI) {
  switch (MI->getOpcode()) {
  default: return false;
  case PPC::ADD: O  << "add ";  printOperand(MI, 0, MVT::i64); O  << ", ";
                 printOperand(MI, 1, MVT::i64); O  << ", "; 
                 printOperand(MI, 2, MVT::i64); O  << '\n'; break;
  case PPC::ADDC: O  << "addc ";  printOperand(MI, 0, MVT::i64); O  << ", ";
                 printOperand(MI, 1, MVT::i64); O  << ", ";
                 printOperand(MI, 2, MVT::i64); O  << '\n'; break;
  case PPC::ADDE: O  << "adde ";  printOperand(MI, 0, MVT::i64); O  << ", ";
                 printOperand(MI, 1, MVT::i64); O  << ", ";
                 printOperand(MI, 2, MVT::i64); O  << '\n'; break;
...

Note that there is one case for each instruction.  Unfortunately, compiling this
function with GCC and optimizations sends GCC spinning and sucking up memory
like crazy.

To help with, it would be nice if the asmwriter generator factored code among
instruction patterns that are identical except for small differences.  In this
case, it would be nice to generate:

  case PPC::ADD:
  case PPC::ADDC:
  case PPC::ADDE:
                 O << OpcodeTable[MI->getOpcode()];
                 printOperand(MI, 0, MVT::i64); O  << ", ";
                 printOperand(MI, 1, MVT::i64); O  << ", ";
                 printOperand(MI, 2, MVT::i64); O  << '\n'; break;

Note that since most targets only have a few different flavors of instruction,
this would dramatically reduce the amount of code in the switch statements. 
This would make the asmwriter generator faster (less to blow the icache) and not
cause GCC to punish our release builds.

-Chris



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