[llvm-branch-commits] [llvm-branch] r347028 - Merging r344591:

Tom Stellard via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Thu Nov 15 21:16:44 PST 2018


Author: tstellar
Date: Thu Nov 15 21:16:44 2018
New Revision: 347028

URL: http://llvm.org/viewvc/llvm-project?rev=347028&view=rev
Log:
Merging r344591:

------------------------------------------------------------------------
r344591 | abeserminji | 2018-10-16 01:27:28 -0700 (Tue, 16 Oct 2018) | 11 lines

[mips][micromips] Fix how values in .gcc_except_table are calculated

When a landing pad is calculated in a program that is compiled
for micromips, it will point to an even address. Such an error will
cause a segmentation fault, as the instructions in micromips are
aligned on odd addresses. This patch sets the last bit of the offset
where a landing pad is, to 1, which will effectively be
an odd address and point to the instruction exactly.

Differential Revision: https://reviews.llvm.org/D52985

------------------------------------------------------------------------

Added:
    llvm/branches/release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll
Modified:
    llvm/branches/release_70/include/llvm/MC/MCAsmBackend.h
    llvm/branches/release_70/lib/MC/MCExpr.cpp
    llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
    llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

Modified: llvm/branches/release_70/include/llvm/MC/MCAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/include/llvm/MC/MCAsmBackend.h?rev=347028&r1=347027&r2=347028&view=diff
==============================================================================
--- llvm/branches/release_70/include/llvm/MC/MCAsmBackend.h (original)
+++ llvm/branches/release_70/include/llvm/MC/MCAsmBackend.h Thu Nov 15 21:16:44 2018
@@ -165,6 +165,11 @@ public:
     return 0;
   }
 
+  /// Check whether a given symbol has been flagged with MICROMIPS flag.
+  virtual bool isMicroMips(const MCSymbol *Sym) const {
+    return false;
+  }
+
   /// Handles all target related code padding when starting to write a new
   /// basic block to an object file.
   ///

Modified: llvm/branches/release_70/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/MC/MCExpr.cpp?rev=347028&r1=347027&r2=347028&view=diff
==============================================================================
--- llvm/branches/release_70/lib/MC/MCExpr.cpp (original)
+++ llvm/branches/release_70/lib/MC/MCExpr.cpp Thu Nov 15 21:16:44 2018
@@ -524,6 +524,11 @@ static void AttemptToFoldSymbolOffsetDif
     if (Asm->isThumbFunc(&SA))
       Addend |= 1;
 
+    // If symbol is labeled as micromips, we set low-bit to ensure
+    // correct offset in .gcc_except_table
+    if (Asm->getBackend().isMicroMips(&SA))
+      Addend |= 1;
+
     // Clear the symbol expr pointers to indicate we have folded these
     // operands.
     A = B = nullptr;

Modified: llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=347028&r1=347027&r2=347028&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original)
+++ llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Thu Nov 15 21:16:44 2018
@@ -25,6 +25,7 @@
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCSymbolELF.h"
 #include "llvm/MC/MCTargetOptions.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -568,6 +569,14 @@ bool MipsAsmBackend::shouldForceRelocati
   }
 }
 
+bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const {
+  if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Sym)) {
+    if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS)
+      return true;
+  }
+  return false;
+}
+
 MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
                                          const MCSubtargetInfo &STI,
                                          const MCRegisterInfo &MRI,

Modified: llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h?rev=347028&r1=347027&r2=347028&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h (original)
+++ llvm/branches/release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Thu Nov 15 21:16:44 2018
@@ -25,6 +25,7 @@ class MCAssembler;
 struct MCFixupKindInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
+class MCSymbolELF;
 class Target;
 
 class MipsAsmBackend : public MCAsmBackend {
@@ -90,6 +91,7 @@ public:
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 
+  bool isMicroMips(const MCSymbol *Sym) const override;
 }; // class MipsAsmBackend
 
 } // namespace

Added: llvm/branches/release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll?rev=347028&view=auto
==============================================================================
--- llvm/branches/release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll (added)
+++ llvm/branches/release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll Thu Nov 15 21:16:44 2018
@@ -0,0 +1,37 @@
+; RUN: llc -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -O3 -filetype=obj < %s | llvm-objdump -s -j .gcc_except_table - | FileCheck %s
+
+; CHECK: Contents of section .gcc_except_table:
+; CHECK-NEXT: 0000 ff9b1501 0c011100 00110e1f 011f1800
+; CHECK-NEXT: 0010 00010000 00000000
+
+ at _ZTIi = external constant i8*
+
+define dso_local i32 @main() local_unnamed_addr norecurse personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
+  %0 = bitcast i8* %exception.i to i32*
+  store i32 5, i32* %0, align 16
+  invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn
+          to label %.noexc unwind label %return
+
+.noexc:
+  unreachable
+
+return:
+  %1 = landingpad { i8*, i32 }
+          catch i8* null
+  %2 = extractvalue { i8*, i32 } %1, 0
+  %3 = tail call i8* @__cxa_begin_catch(i8* %2) nounwind
+  tail call void @__cxa_end_catch()
+  ret i32 0
+}
+
+declare i32 @__gxx_personality_v0(...)
+
+declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr
+
+declare void @__cxa_end_catch() local_unnamed_addr
+
+declare i8* @__cxa_allocate_exception(i32) local_unnamed_addr
+
+declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr




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