[llvm-branch-commits] [llvm-branch] r346741 - Merging r342884:
Tom Stellard via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Nov 12 21:58:13 PST 2018
Author: tstellar
Date: Mon Nov 12 21:58:13 2018
New Revision: 346741
URL: http://llvm.org/viewvc/llvm-project?rev=346741&view=rev
Log:
Merging r342884:
------------------------------------------------------------------------
r342884 | petarj | 2018-09-24 07:14:19 -0700 (Mon, 24 Sep 2018) | 12 lines
[Mips][FastISel] Fix selectBranch on icmp i1
The r337288 tried to fix result of icmp i1 when its input is not sanitized
by falling back to DagISel. While it now produces the correct result for
bit 0, the other bits can still hold arbitrary value which is not supported
by MipsFastISel branch lowering. This patch fixes the issue by falling back
to DagISel in this case.
Patch by Dragan Mladjenovic.
Differential Revision: https://reviews.llvm.org/D52045
------------------------------------------------------------------------
Added:
llvm/branches/release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
Modified:
llvm/branches/release_70/lib/Target/Mips/MipsFastISel.cpp
Modified: llvm/branches/release_70/lib/Target/Mips/MipsFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/Mips/MipsFastISel.cpp?rev=346741&r1=346740&r2=346741&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/branches/release_70/lib/Target/Mips/MipsFastISel.cpp Mon Nov 12 21:58:13 2018
@@ -953,6 +953,11 @@ bool MipsFastISel::selectBranch(const In
MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
// For now, just try the simplest case where it's fed by a compare.
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
+ MVT CIMVT =
+ TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT();
+ if (CIMVT == MVT::i1)
+ return false;
+
unsigned CondReg = getRegForValue(CI);
BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
.addReg(CondReg)
Added: llvm/branches/release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll?rev=346741&view=auto
==============================================================================
--- llvm/branches/release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll (added)
+++ llvm/branches/release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll Mon Nov 12 21:58:13 2018
@@ -0,0 +1,189 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN: < %s -verify-machineinstrs | FileCheck %s
+
+define void @testeq(i32, i32) {
+; CHECK-LABEL: testeq:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: beq $[[REG0]], $[[REG1]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp eq i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testne(i32, i32) {
+; CHECK-LABEL: testne:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: bne $[[REG0]], $[[REG1]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp ne i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testugt(i32, i32) {
+; CHECK-LABEL: testugt:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
+; CHECK: bnez $[[REG2]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp ugt i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testuge(i32, i32) {
+; CHECK-LABEL: testuge:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
+; CHECK: beqz $[[REG2]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp uge i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testult(i32, i32) {
+; CHECK-LABEL: testult:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
+; CHECK: bnez $[[REG2]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp ult i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testule(i32, i32) {
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
+; CHECK: beqz $[[REG2]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp ule i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testsgt(i32, i32) {
+; CHECK-LABEL: testsgt:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: negu $[[REG0]], $[[REG0]]
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: negu $[[REG1]], $[[REG1]]
+; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
+; CHECK: bnez $[[REG2]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp sgt i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testsge(i32, i32) {
+; CHECK-LABEL: testsge:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: negu $[[REG0]], $[[REG0]]
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: negu $[[REG1]], $[[REG1]]
+; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
+; CHECK: beqz $[[REG2]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp sge i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testslt(i32, i32) {
+; CHECK-LABEL: testslt:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: negu $[[REG0]], $[[REG0]]
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: negu $[[REG1]], $[[REG1]]
+; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
+; CHECK: bnez $[[REG2]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp slt i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+define void @testsle(i32, i32) {
+; CHECK-LABEL: testsle:
+; CHECK: andi $[[REG0:[0-9]+]], $4, 1
+; CHECK: negu $[[REG0]], $[[REG0]]
+; CHECK: andi $[[REG1:[0-9]+]], $5, 1
+; CHECK: negu $[[REG1]], $[[REG1]]
+; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
+; CHECK: beqz $[[REG2]],
+ %3 = trunc i32 %0 to i1
+ %4 = trunc i32 %1 to i1
+ %5 = icmp sle i1 %3, %4
+ br i1 %5, label %end, label %trap
+trap:
+ call void @llvm.trap()
+ br label %end
+end:
+ ret void
+}
+
+
+declare void @llvm.trap()
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