[llvm-branch-commits] [llvm-branch] r323772 - Merging r323706:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Jan 30 07:29:20 PST 2018
Author: hans
Date: Tue Jan 30 07:29:20 2018
New Revision: 323772
URL: http://llvm.org/viewvc/llvm-project?rev=323772&view=rev
Log:
Merging r323706:
------------------------------------------------------------------------
r323706 | mareko | 2018-01-30 00:19:10 +0100 (Tue, 30 Jan 2018) | 15 lines
AMDGPU: Allow a SGPR for the conditional KILL operand
Patch by: Bas Nieuwenhuizen
Just use the _e64 variant if needed. This should be possible as per
def : Pat <
(int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))),
(SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond))
> ;
I don't think we can get an immediate for the other operand for which we
need the second 32-bit word.
https://reviews.llvm.org/D42302
------------------------------------------------------------------------
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/AMDGPU/SIInsertSkips.cpp
llvm/branches/release_60/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
Propchange: llvm/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Jan 30 07:29:20 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323190,323307,323331,323355,323369,323371,323384,323469,323515,323582,323671-323672,323710
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323190,323307,323331,323355,323369,323371,323384,323469,323515,323582,323671-323672,323706,323710
Modified: llvm/branches/release_60/lib/Target/AMDGPU/SIInsertSkips.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AMDGPU/SIInsertSkips.cpp?rev=323772&r1=323771&r2=323772&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AMDGPU/SIInsertSkips.cpp (original)
+++ llvm/branches/release_60/lib/Target/AMDGPU/SIInsertSkips.cpp Tue Jan 30 07:29:20 2018
@@ -210,65 +210,73 @@ void SIInsertSkips::kill(MachineInstr &M
switch (MI.getOperand(2).getImm()) {
case ISD::SETOEQ:
case ISD::SETEQ:
- Opcode = AMDGPU::V_CMPX_EQ_F32_e32;
+ Opcode = AMDGPU::V_CMPX_EQ_F32_e64;
break;
case ISD::SETOGT:
case ISD::SETGT:
- Opcode = AMDGPU::V_CMPX_LT_F32_e32;
+ Opcode = AMDGPU::V_CMPX_LT_F32_e64;
break;
case ISD::SETOGE:
case ISD::SETGE:
- Opcode = AMDGPU::V_CMPX_LE_F32_e32;
+ Opcode = AMDGPU::V_CMPX_LE_F32_e64;
break;
case ISD::SETOLT:
case ISD::SETLT:
- Opcode = AMDGPU::V_CMPX_GT_F32_e32;
+ Opcode = AMDGPU::V_CMPX_GT_F32_e64;
break;
case ISD::SETOLE:
case ISD::SETLE:
- Opcode = AMDGPU::V_CMPX_GE_F32_e32;
+ Opcode = AMDGPU::V_CMPX_GE_F32_e64;
break;
case ISD::SETONE:
case ISD::SETNE:
- Opcode = AMDGPU::V_CMPX_LG_F32_e32;
+ Opcode = AMDGPU::V_CMPX_LG_F32_e64;
break;
case ISD::SETO:
- Opcode = AMDGPU::V_CMPX_O_F32_e32;
+ Opcode = AMDGPU::V_CMPX_O_F32_e64;
break;
case ISD::SETUO:
- Opcode = AMDGPU::V_CMPX_U_F32_e32;
+ Opcode = AMDGPU::V_CMPX_U_F32_e64;
break;
case ISD::SETUEQ:
- Opcode = AMDGPU::V_CMPX_NLG_F32_e32;
+ Opcode = AMDGPU::V_CMPX_NLG_F32_e64;
break;
case ISD::SETUGT:
- Opcode = AMDGPU::V_CMPX_NGE_F32_e32;
+ Opcode = AMDGPU::V_CMPX_NGE_F32_e64;
break;
case ISD::SETUGE:
- Opcode = AMDGPU::V_CMPX_NGT_F32_e32;
+ Opcode = AMDGPU::V_CMPX_NGT_F32_e64;
break;
case ISD::SETULT:
- Opcode = AMDGPU::V_CMPX_NLE_F32_e32;
+ Opcode = AMDGPU::V_CMPX_NLE_F32_e64;
break;
case ISD::SETULE:
- Opcode = AMDGPU::V_CMPX_NLT_F32_e32;
+ Opcode = AMDGPU::V_CMPX_NLT_F32_e64;
break;
case ISD::SETUNE:
- Opcode = AMDGPU::V_CMPX_NEQ_F32_e32;
+ Opcode = AMDGPU::V_CMPX_NEQ_F32_e64;
break;
default:
llvm_unreachable("invalid ISD:SET cond code");
}
- // TODO: Allow this:
- if (!MI.getOperand(0).isReg() ||
- !TRI->isVGPR(MBB.getParent()->getRegInfo(),
- MI.getOperand(0).getReg()))
- llvm_unreachable("SI_KILL operand should be a VGPR");
+ assert(MI.getOperand(0).isReg());
- BuildMI(MBB, &MI, DL, TII->get(Opcode))
- .add(MI.getOperand(1))
- .add(MI.getOperand(0));
+ if (TRI->isVGPR(MBB.getParent()->getRegInfo(),
+ MI.getOperand(0).getReg())) {
+ Opcode = AMDGPU::getVOPe32(Opcode);
+ BuildMI(MBB, &MI, DL, TII->get(Opcode))
+ .add(MI.getOperand(1))
+ .add(MI.getOperand(0));
+ } else {
+ BuildMI(MBB, &MI, DL, TII->get(Opcode))
+ .addReg(AMDGPU::VCC, RegState::Define)
+ .addImm(0) // src0 modifiers
+ .add(MI.getOperand(1))
+ .addImm(0) // src1 modifiers
+ .add(MI.getOperand(0))
+ .addImm(0); // omod
+ }
break;
}
case AMDGPU::SI_KILL_I1_TERMINATOR: {
Modified: llvm/branches/release_60/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll?rev=323772&r1=323771&r2=323772&view=diff
==============================================================================
--- llvm/branches/release_60/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll (original)
+++ llvm/branches/release_60/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll Tue Jan 30 07:29:20 2018
@@ -234,6 +234,23 @@ define amdgpu_ps void @wqm(float %a) {
ret void
}
+; This checks that we use the 64-bit encoding when the operand is a SGPR.
+; SI-LABEL: {{^}}test_sgpr:
+; SI: v_cmpx_ge_f32_e64
+define amdgpu_ps void @test_sgpr(float inreg %a) #0 {
+ %c = fcmp ole float %a, 1.000000e+00
+ call void @llvm.amdgcn.kill(i1 %c) #1
+ ret void
+}
+
+; SI-LABEL: {{^}}test_non_inline_imm_sgpr:
+; SI-NOT: v_cmpx_ge_f32_e64
+define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 {
+ %c = fcmp ole float %a, 1.500000e+00
+ call void @llvm.amdgcn.kill(i1 %c) #1
+ ret void
+}
+
declare void @llvm.amdgcn.kill(i1) #0
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
declare i1 @llvm.amdgcn.wqm.vote(i1)
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