[llvm-branch-commits] [llvm-branch] r323746 - Merging r323710:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Tue Jan 30 02:53:45 2018
New Revision: 323746

URL: http://llvm.org/viewvc/llvm-project?rev=323746&view=rev
Log:
Merging r323710:
------------------------------------------------------------------------
r323710 | qcolombet | 2018-01-30 00:42:37 +0100 (Tue, 30 Jan 2018) | 13 lines

[RAFast] Don't dereference MBB::end

When RAFast sees liveins in on a basic block, it uses that information
to initialize the availability of the registers. The called
method uses an instruction as one of its argument and in the liveins
case, RAFast was dereferencing MBB::begin which can be MBB::end for
empty basic block.

Change the API of definePhysReg to use MachineBasicBlock::iterator
instead of MachineInstr so that we don't dereference an
invalid iterator while making the call.

rdar://problem/36952401
------------------------------------------------------------------------

Added:
    llvm/branches/release_60/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
      - copied unchanged from r323710, llvm/trunk/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
Modified:
    llvm/branches/release_60/   (props changed)
    llvm/branches/release_60/lib/CodeGen/RegAllocFast.cpp

Propchange: llvm/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Jan 30 02:53:45 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323190,323307,323331,323369,323371,323384,323582,323671-323672
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323190,323307,323331,323369,323371,323384,323582,323671-323672,323710

Modified: llvm/branches/release_60/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/CodeGen/RegAllocFast.cpp?rev=323746&r1=323745&r2=323746&view=diff
==============================================================================
--- llvm/branches/release_60/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/branches/release_60/lib/CodeGen/RegAllocFast.cpp Tue Jan 30 02:53:45 2018
@@ -193,9 +193,10 @@ namespace {
     void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
 
     void usePhysReg(MachineOperand &MO);
-    void definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, RegState NewState);
+    void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg,
+                       RegState NewState);
     unsigned calcSpillCost(MCPhysReg PhysReg) const;
-    void assignVirtToPhysReg(LiveReg&, MCPhysReg PhysReg);
+    void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);
 
     LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
       return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
@@ -434,8 +435,8 @@ void RegAllocFast::usePhysReg(MachineOpe
 /// Mark PhysReg as reserved or free after spilling any virtregs. This is very
 /// similar to defineVirtReg except the physreg is reserved instead of
 /// allocated.
-void RegAllocFast::definePhysReg(MachineInstr &MI, MCPhysReg PhysReg,
-                                 RegState NewState) {
+void RegAllocFast::definePhysReg(MachineBasicBlock::iterator MI,
+                                 MCPhysReg PhysReg, RegState NewState) {
   markRegUsedInInstr(PhysReg);
   switch (unsigned VirtReg = PhysRegState[PhysReg]) {
   case regDisabled:
@@ -857,7 +858,7 @@ void RegAllocFast::allocateBasicBlock(Ma
   // Add live-in registers as live.
   for (const MachineBasicBlock::RegisterMaskPair LI : MBB.liveins())
     if (MRI->isAllocatable(LI.PhysReg))
-      definePhysReg(*MII, LI.PhysReg, regReserved);
+      definePhysReg(MII, LI.PhysReg, regReserved);
 
   VirtDead.clear();
   Coalesced.clear();