[llvm-branch-commits] [llvm-branch] r325709 - [ReleaseNotes] Initial release notes for X86 target.

[Craig Topper via llvm-branch-commits]

Author: ctopper
Date: Wed Feb 21 11:27:01 2018
New Revision: 325709

URL: http://llvm.org/viewvc/llvm-project?rev=325709&view=rev
Log:
[ReleaseNotes] Initial release notes for X86 target.

Modified:
    llvm/branches/release_60/docs/ReleaseNotes.rst

Modified: llvm/branches/release_60/docs/ReleaseNotes.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/docs/ReleaseNotes.rst?rev=325709&r1=325708&r2=325709&view=diff
==============================================================================
--- llvm/branches/release_60/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_60/docs/ReleaseNotes.rst Wed Feb 21 11:27:01 2018
@@ -135,11 +135,23 @@ During this release the SystemZ target h
 Changes to the X86 Target
 -------------------------
 
-During this release ...
+During this release the X86 target has:
 
-* Got support for enabling SjLj exception handling on platforms where it
+* Added support for enabling SjLj exception handling on platforms where it
   isn't the default.
 
+* Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI.
+
+* Added support for Intel Icelake CPU.
+
+* Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs.
+
+* Improved codegen of data being transferred between GPRs and K-registers.
+
+* Improved llvm-mc's disassembler for some EVEX encoded instructions.
+
+* Improved codegen for vector truncations.
+
 Changes to the AMDGPU Target
 -----------------------------