[llvm-branch-commits] [llvm-branch] r325007 - Merging r324746:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Feb 13 06:42:24 PST 2018
Author: hans
Date: Tue Feb 13 06:42:24 2018
New Revision: 325007
URL: http://llvm.org/viewvc/llvm-project?rev=325007&view=rev
Log:
Merging r324746:
------------------------------------------------------------------------
r324746 | arsenm | 2018-02-09 17:57:48 +0100 (Fri, 09 Feb 2018) | 4 lines
AMDGPU: Fix layering issue
Move utility function that depends on codegen.
Fixes build with r324487 reapplied.
------------------------------------------------------------------------
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.h
llvm/branches/release_60/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/branches/release_60/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Propchange: llvm/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 06:42:24 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324772
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324746,324772
Modified: llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp?rev=325007&r1=325006&r2=325007&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp (original)
+++ llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp Tue Feb 13 06:42:24 2018
@@ -108,3 +108,21 @@ int AMDGPUInstrInfo::pseudoToMCOpcode(in
return MCOp;
}
+
+// TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence.
+bool AMDGPUInstrInfo::isUniformMMO(const MachineMemOperand *MMO) {
+ const Value *Ptr = MMO->getValue();
+ // UndefValue means this is a load of a kernel input. These are uniform.
+ // Sometimes LDS instructions have constant pointers.
+ // If Ptr is null, then that means this mem operand contains a
+ // PseudoSourceValue like GOT.
+ if (!Ptr || isa<UndefValue>(Ptr) ||
+ isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
+ return true;
+
+ if (const Argument *Arg = dyn_cast<Argument>(Ptr))
+ return AMDGPU::isArgPassedInSGPR(Arg);
+
+ const Instruction *I = dyn_cast<Instruction>(Ptr);
+ return I && I->getMetadata("amdgpu.uniform");
+}
Modified: llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.h?rev=325007&r1=325006&r2=325007&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.h (original)
+++ llvm/branches/release_60/lib/Target/AMDGPU/AMDGPUInstrInfo.h Tue Feb 13 06:42:24 2018
@@ -50,6 +50,8 @@ public:
/// Return -1 if the target-specific opcode for the pseudo instruction does
/// not exist. If Opcode is not a pseudo instruction, this is identity.
int pseudoToMCOpcode(int Opcode) const;
+
+ static bool isUniformMMO(const MachineMemOperand *MMO);
};
} // End llvm namespace
Modified: llvm/branches/release_60/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=325007&r1=325006&r2=325007&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/branches/release_60/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Tue Feb 13 06:42:24 2018
@@ -120,7 +120,7 @@ static bool isInstrUniform(const Machine
return false;
const MachineMemOperand *MMO = *MI.memoperands_begin();
- return AMDGPU::isUniformMMO(MMO);
+ return AMDGPUInstrInfo::isUniformMMO(MMO);
}
const RegisterBankInfo::InstructionMapping &
Modified: llvm/branches/release_60/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AMDGPU/SIISelLowering.cpp?rev=325007&r1=325006&r2=325007&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/AMDGPU/SIISelLowering.cpp Tue Feb 13 06:42:24 2018
@@ -1086,7 +1086,7 @@ bool SITargetLowering::isCheapAddrSpaceC
bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
const MemSDNode *MemNode = cast<MemSDNode>(N);
- return AMDGPU::isUniformMMO(MemNode->getMemOperand());
+ return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
}
TargetLoweringBase::LegalizeTypeAction
Modified: llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=325007&r1=325006&r2=325007&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)
+++ llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Tue Feb 13 06:42:24 2018
@@ -871,24 +871,6 @@ bool isArgPassedInSGPR(const Argument *A
}
}
-// TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence.
-bool isUniformMMO(const MachineMemOperand *MMO) {
- const Value *Ptr = MMO->getValue();
- // UndefValue means this is a load of a kernel input. These are uniform.
- // Sometimes LDS instructions have constant pointers.
- // If Ptr is null, then that means this mem operand contains a
- // PseudoSourceValue like GOT.
- if (!Ptr || isa<UndefValue>(Ptr) ||
- isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
- return true;
-
- if (const Argument *Arg = dyn_cast<Argument>(Ptr))
- return isArgPassedInSGPR(Arg);
-
- const Instruction *I = dyn_cast<Instruction>(Ptr);
- return I && I->getMetadata("amdgpu.uniform");
-}
-
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
if (isGCN3Encoding(ST))
return ByteOffset;
Modified: llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=325007&r1=325006&r2=325007&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (original)
+++ llvm/branches/release_60/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h Tue Feb 13 06:42:24 2018
@@ -363,7 +363,6 @@ LLVM_READNONE
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
bool isArgPassedInSGPR(const Argument *Arg);
-bool isUniformMMO(const MachineMemOperand *MMO);
/// \returns The encoding that will be used for \p ByteOffset in the SMRD
/// offset field.
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