[llvm-branch-commits] [llvm-branch] r314327 - Merging r312337:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Wed Sep 27 11:08:25 2017
New Revision: 314327

URL: http://llvm.org/viewvc/llvm-project?rev=314327&view=rev
Log:
Merging r312337:

------------------------------------------------------------------------
r312337 | nha | 2017-09-01 09:56:32 -0700 (Fri, 01 Sep 2017) | 12 lines

AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states

Summary:
This fixes a bug that was exposed on gfx9 in various
GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests,
e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment

Reviewers: arsenm

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D36193
------------------------------------------------------------------------

Added:
    llvm/branches/release_50/test/CodeGen/AMDGPU/hazard.mir
Modified:
    llvm/branches/release_50/   (props changed)
    llvm/branches/release_50/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Propchange: llvm/branches/release_50/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Sep 27 11:08:25 2017
@@ -1 +1 @@
-/llvm/trunk:312337
+/llvm/trunk:155241,308483-308484,308503,308808,308813,308847,308891,308906,308950,308963,308978,308986,309044,309071,309113,309120,309122,309140,309227,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309614,309651,309744,309758,309849,309928,309930,309945,310066,310071,310190,310240-310242,310250,310253,310262,310267,310481,310492,310498,310510,310534,310552,310604,310712,310779,310784,310796,310842,310906,310926,310939,310979,310988,310990-310991,311061,311068,311071,311087,311229,311258,311263,311387,311429,311554,311565,311572,311623,311835,312022,312285,313334:312337

Modified: llvm/branches/release_50/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AMDGPU/GCNHazardRecognizer.cpp?rev=314327&r1=314326&r2=314327&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (original)
+++ llvm/branches/release_50/lib/Target/AMDGPU/GCNHazardRecognizer.cpp Wed Sep 27 11:08:25 2017
@@ -218,12 +218,17 @@ void GCNHazardRecognizer::RecedeCycle()
 
 int GCNHazardRecognizer::getWaitStatesSince(
     function_ref<bool(MachineInstr *)> IsHazard) {
-  int WaitStates = -1;
+  int WaitStates = 0;
   for (MachineInstr *MI : EmittedInstrs) {
+    if (MI) {
+      if (IsHazard(MI))
+        return WaitStates;
+
+      unsigned Opcode = MI->getOpcode();
+      if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF)
+        continue;
+    }
     ++WaitStates;
-    if (!MI || !IsHazard(MI))
-      continue;
-    return WaitStates;
   }
   return std::numeric_limits<int>::max();
 }

Added: llvm/branches/release_50/test/CodeGen/AMDGPU/hazard.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AMDGPU/hazard.mir?rev=314327&view=auto
==============================================================================
--- llvm/branches/release_50/test/CodeGen/AMDGPU/hazard.mir (added)
+++ llvm/branches/release_50/test/CodeGen/AMDGPU/hazard.mir Wed Sep 27 11:08:25 2017
@@ -0,0 +1,31 @@
+# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
+
+# GCN:    bb.0.entry:
+# GCN:      %m0 = S_MOV_B32
+# GFX9:     S_NOP 0
+# VI-NOT:   S_NOP_0
+# GCN:      V_INTERP_P1_F32
+
+---
+name:            hazard_implicit_def
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '%sgpr7', virtual-reg: '' }
+  - { reg: '%vgpr4', virtual-reg: '' }
+body:             |
+  bb.0.entry:
+    liveins: %sgpr7, %vgpr4
+
+    %m0 = S_MOV_B32 killed %sgpr7
+    %vgpr5 = IMPLICIT_DEF
+    %vgpr0 = V_INTERP_P1_F32 killed %vgpr4, 0, 0, implicit %m0, implicit %exec
+    SI_RETURN_TO_EPILOG killed %vgpr5, killed %vgpr0
+
+...