[llvm-branch-commits] [llvm-branch] r319231 - Merging r316035:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Tue Nov 28 14:02:15 2017
New Revision: 319231

URL: http://llvm.org/viewvc/llvm-project?rev=319231&view=rev
Log:
Merging r316035:

------------------------------------------------------------------------
r316035 | tnorthover | 2017-10-17 14:43:52 -0700 (Tue, 17 Oct 2017) | 6 lines

AArch64: account for possible frame index operand in compares.

If the address of a local is used in a comparison, AArch64 can fold the
address-calculation into the comparison via "adds". Unfortunately, a couple of
places (both hit in this one test) are not ready to deal with that yet and just
assume the first source operand is a register.
------------------------------------------------------------------------

Added:
    llvm/branches/release_50/test/CodeGen/AArch64/cmp-frameindex.ll
Modified:
    llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.cpp
    llvm/branches/release_50/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

Modified: llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=319231&r1=319230&r2=319231&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Nov 28 14:02:15 2017
@@ -940,6 +940,12 @@ bool AArch64InstrInfo::areMemAccessesTri
 bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                                       unsigned &SrcReg2, int &CmpMask,
                                       int &CmpValue) const {
+  // The first operand can be a frame index where we'd normally expect a
+  // register.
+  assert(MI.getNumOperands() >= 2 && "All AArch64 cmps should have 2 operands");
+  if (!MI.getOperand(1).isReg())
+    return false;
+
   switch (MI.getOpcode()) {
   default:
     break;

Modified: llvm/branches/release_50/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp?rev=319231&r1=319230&r2=319231&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp (original)
+++ llvm/branches/release_50/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp Tue Nov 28 14:02:15 2017
@@ -167,6 +167,9 @@ AArch64RedundantCopyElimination::knownRe
     // CMP is an alias for SUBS with a dead destination register.
     case AArch64::SUBSWri:
     case AArch64::SUBSXri: {
+      // Sometimes the first operand is a FrameIndex. Bail if tht happens.
+      if (!PredI.getOperand(1).isReg())
+        return None;
       MCPhysReg SrcReg = PredI.getOperand(1).getReg();
 
       // Must not be a symbolic immediate.

Added: llvm/branches/release_50/test/CodeGen/AArch64/cmp-frameindex.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AArch64/cmp-frameindex.ll?rev=319231&view=auto
==============================================================================
--- llvm/branches/release_50/test/CodeGen/AArch64/cmp-frameindex.ll (added)
+++ llvm/branches/release_50/test/CodeGen/AArch64/cmp-frameindex.ll Tue Nov 28 14:02:15 2017
@@ -0,0 +1,19 @@
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
+
+; CHECK: test_frameindex_cmp:
+; CHECK: cmn sp, #{{[0-9]+}}
+define void @test_frameindex_cmp() {
+  %stack = alloca i8
+  %stack.int = ptrtoint i8* %stack to i64
+  %cmp = icmp ne i64 %stack.int, 0
+  br i1 %cmp, label %bb1, label %bb2
+
+bb1:
+  call void @bar()
+  ret void
+
+bb2:
+  ret void
+}
+
+declare void @bar()