[llvm-branch-commits] [llvm-branch] r309587 - Merging r309325:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Mon Jul 31 10:19:51 2017
New Revision: 309587

URL: http://llvm.org/viewvc/llvm-project?rev=309587&view=rev
Log:
Merging r309325:
------------------------------------------------------------------------
r309325 | ab | 2017-07-27 14:28:59 -0700 (Thu, 27 Jul 2017) | 8 lines

[X86] Don't lie about legality to TLI's demanded bits.

Like r309323, X86 had a typo where it passed the wrong flags to TLO.

Found by inspection; I haven't been able to tickle this into having
observable behavior.  I don't think it does, given that X86 doesn't have
custom demanded bits logic, and the generic logic doesn't have a lot of
exposure to illegal constructs.
------------------------------------------------------------------------

Modified:
    llvm/branches/release_50/   (props changed)
    llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp

Propchange: llvm/branches/release_50/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Jul 31 10:19:51 2017
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309113,309302,309323,309343,309353,309355,309422
+/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309113,309302,309323,309325,309343,309353,309355,309422

Modified: llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp?rev=309587&r1=309586&r2=309587&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp Mon Jul 31 10:19:51 2017
@@ -30612,8 +30612,8 @@ static SDValue combineSelect(SDNode *N,
     assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
     APInt DemandedMask(APInt::getSignMask(BitWidth));
     KnownBits Known;
-    TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
-                                          DCI.isBeforeLegalizeOps());
+    TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
+                                          !DCI.isBeforeLegalizeOps());
     if (TLI.ShrinkDemandedConstant(Cond, DemandedMask, TLO) ||
         TLI.SimplifyDemandedBits(Cond, DemandedMask, Known, TLO)) {
       // If we changed the computation somewhere in the DAG, this change will