[llvm-branch-commits] [llvm-branch] r309348 - Merging r309302:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Thu Jul 27 18:32:26 2017
New Revision: 309348

URL: http://llvm.org/viewvc/llvm-project?rev=309348&view=rev
Log:
Merging r309302:
------------------------------------------------------------------------
r309302 | rksimon | 2017-07-27 11:15:54 -0700 (Thu, 27 Jul 2017) | 3 lines

[SelectionDAG] Improve DAGTypeLegalizer::convertMask assertion (PR33960)

Improve DAGTypeLegalizer::convertMask's isSETCCorConvertedSETCC assertion to properly check for any mixture of SETCC or BUILD_VECTOR of constants, or a logical mask op of them.
------------------------------------------------------------------------

Added:
    llvm/branches/release_50/test/CodeGen/X86/pr33960.ll
      - copied unchanged from r309302, llvm/trunk/test/CodeGen/X86/pr33960.ll
Modified:
    llvm/branches/release_50/   (props changed)
    llvm/branches/release_50/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Propchange: llvm/branches/release_50/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Jul 27 18:32:26 2017
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986
+/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309302

Modified: llvm/branches/release_50/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=309348&r1=309347&r2=309348&view=diff
==============================================================================
--- llvm/branches/release_50/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/branches/release_50/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Jul 27 18:32:26 2017
@@ -2965,7 +2965,12 @@ static inline bool isSETCCorConvertedSET
   else if (N.getOpcode() == ISD::SIGN_EXTEND)
     N = N.getOperand(0);
 
-  return (N.getOpcode() == ISD::SETCC);
+  if (isLogicalMaskOp(N.getOpcode()))
+    return isSETCCorConvertedSETCC(N.getOperand(0)) &&
+           isSETCCorConvertedSETCC(N.getOperand(1));
+
+  return (N.getOpcode() == ISD::SETCC ||
+          ISD::isBuildVectorOfConstantSDNodes(N.getNode()));
 }
 #endif
 
@@ -2973,28 +2978,20 @@ static inline bool isSETCCorConvertedSET
 // to ToMaskVT if needed with vector extension or truncation.
 SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
                                       EVT ToMaskVT) {
-  LLVMContext &Ctx = *DAG.getContext();
-
   // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
-  unsigned InMaskOpc = InMask->getOpcode();
-
   // FIXME: This code seems to be too restrictive, we might consider
   // generalizing it or dropping it.
-  assert((InMaskOpc == ISD::SETCC ||
-          ISD::isBuildVectorOfConstantSDNodes(InMask.getNode()) ||
-          (isLogicalMaskOp(InMaskOpc) &&
-           isSETCCorConvertedSETCC(InMask->getOperand(0)) &&
-           isSETCCorConvertedSETCC(InMask->getOperand(1)))) &&
-         "Unexpected mask argument.");
+  assert(isSETCCorConvertedSETCC(InMask) && "Unexpected mask argument.");
 
   // Make a new Mask node, with a legal result VT.
   SmallVector<SDValue, 4> Ops;
   for (unsigned i = 0; i < InMask->getNumOperands(); ++i)
     Ops.push_back(InMask->getOperand(i));
-  SDValue Mask = DAG.getNode(InMaskOpc, SDLoc(InMask), MaskVT, Ops);
+  SDValue Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
 
   // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
   // extend or truncate is needed.
+  LLVMContext &Ctx = *DAG.getContext();
   unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
   unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
   if (MaskScalarBits < ToMaskScalBits) {