[llvm-branch-commits] [llvm-branch] r310899 - Merging r310784:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Mon Aug 14 17:09:10 2017
New Revision: 310899

URL: http://llvm.org/viewvc/llvm-project?rev=310899&view=rev
Log:
Merging r310784:
------------------------------------------------------------------------
r310784 | ctopper | 2017-08-12 13:19:44 -0700 (Sat, 12 Aug 2017) | 16 lines

[X86] When handling addcarry intrinsic, create the flag result with the correct type so we don't crash if we use a memory instruction

Summary:
Previously we were creating the flag result with MVT::Other which is interpretted as a Chain node. If we used a memory form of the instruction we would end up with a copyToReg that consumed the chain result of the adcx instruction instead of the flag result.

Pretty sure we should be using MVT::i32 here, that's what we do other places we create these node types.

We should probably consider this for 5.0 as well.

Reviewers: RKSimon, zvi, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36645
------------------------------------------------------------------------

Modified:
    llvm/branches/release_50/   (props changed)
    llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/release_50/test/CodeGen/X86/adx-intrinsics.ll

Propchange: llvm/branches/release_50/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Aug 14 17:09:10 2017
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,308483-308484,308503,308808,308813,308847,308891,308906,308950,308963,308978,308986,309044,309071,309113,309120,309122,309140,309227,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309614,309651,309744,309758,309849,309928,309930,309945,310071,310190,310240-310242,310250,310253,310267,310481,310492,310510,310534,310552,310604,310779,310842
+/llvm/trunk:155241,308483-308484,308503,308808,308813,308847,308891,308906,308950,308963,308978,308986,309044,309071,309113,309120,309122,309140,309227,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309614,309651,309744,309758,309849,309928,309930,309945,310071,310190,310240-310242,310250,310253,310267,310481,310492,310510,310534,310552,310604,310779,310784,310842

Modified: llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp?rev=310899&r1=310898&r2=310899&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp Mon Aug 14 17:09:10 2017
@@ -20671,8 +20671,8 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
   }
   // ADC/ADCX/SBB
   case ADX: {
-    SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
-    SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
+    SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
+    SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::i32);
     SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
                                 DAG.getConstant(-1, dl, MVT::i8));
     SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),

Modified: llvm/branches/release_50/test/CodeGen/X86/adx-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/X86/adx-intrinsics.ll?rev=310899&r1=310898&r2=310899&view=diff
==============================================================================
--- llvm/branches/release_50/test/CodeGen/X86/adx-intrinsics.ll (original)
+++ llvm/branches/release_50/test/CodeGen/X86/adx-intrinsics.ll Mon Aug 14 17:09:10 2017
@@ -75,3 +75,30 @@ define i8 @test_subborrow_u64(i8 %c, i64
   ret i8 %ret;
 }
 
+; Try a version with loads. Previously we crashed on this.
+define i32 @load_crash(i64* nocapture readonly %a, i64* nocapture readonly %b, i64* %res)  {
+; CHECK-LABEL: load_crash
+; CHECK: addb
+; ADX: adcxq
+; CHECK: setb
+; CHECK: retq
+  %1 = load i64, i64* %a, align 8
+  %2 = load i64, i64* %b, align 8
+  %3 = bitcast i64* %res to i8*
+  %4 = tail call i8 @llvm.x86.addcarryx.u64(i8 0, i64 %1, i64 %2, i8* %3)
+  %conv = zext i8 %4 to i32
+  ret i32 %conv
+}
+
+; Try a really simple all zero input case, which also used to crash
+define void @allzeros() {
+; CHECK-LABEL: allzeros
+; CHECK: xorl
+; CHECK: addb
+; CHECK: sbbq
+; CHECK: andl
+; CHECK: retq
+entry:
+  %0 = tail call i8 @llvm.x86.addcarryx.u64(i8 0, i64 0, i64 0, i8* null)
+  ret void
+}