[llvm-branch-commits] [llvm-branch] r310293 - Merging r310190:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Mon Aug  7 13:14:13 2017
New Revision: 310293

URL: http://llvm.org/viewvc/llvm-project?rev=310293&view=rev
Log:
Merging r310190:
------------------------------------------------------------------------
r310190 | ctopper | 2017-08-05 16:34:44 -0700 (Sat, 05 Aug 2017) | 18 lines

[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled

Summary:
On older processors this instruction encoding is treated as a NOP.

MSVC doesn't disable intrinsics based on features the way clang/gcc does. Because the PAUSE instruction encoding doesn't crash older processors, some software out there uses these intrinsics without checking for SSE2.

This change also seems to also be consistent with gcc behavior.

Fixes PR34079

Reviewers: RKSimon, zvi

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36361
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Added:
    llvm/branches/release_50/test/CodeGen/X86/pause.ll
      - copied unchanged from r310190, llvm/trunk/test/CodeGen/X86/pause.ll
Modified:
    llvm/branches/release_50/   (props changed)
    llvm/branches/release_50/lib/Target/X86/X86InstrSSE.td

Propchange: llvm/branches/release_50/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Aug  7 13:14:13 2017
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309113,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309651,309744,309849,309928,309930,310071
+/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309113,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309651,309744,309849,309928,309930,310071,310190

Modified: llvm/branches/release_50/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86InstrSSE.td?rev=310293&r1=310292&r2=310293&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/release_50/lib/Target/X86/X86InstrSSE.td Mon Aug  7 13:14:13 2017
@@ -3697,8 +3697,7 @@ let SchedRW = [WriteNop] in {
 // Pause. This "instruction" is encoded as "rep; nop", so even though it
 // was introduced with SSE2, it's backward compatible.
 def PAUSE : I<0x90, RawFrm, (outs), (ins),
-              "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
-              OBXS, Requires<[HasSSE2]>;
+              "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>, OBXS;
 }
 
 let SchedRW = [WriteFence] in {