[llvm-branch-commits] [llvm-branch] r301437 - Merging r300429:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Wed Apr 26 12:52:15 2017
New Revision: 301437

URL: http://llvm.org/viewvc/llvm-project?rev=301437&view=rev
Log:
Merging r300429:

------------------------------------------------------------------------
r300429 | d0k | 2017-04-16 16:13:08 -0400 (Sun, 16 Apr 2017) | 7 lines

[X86] Remove special handling for 16 bit for A asm constraints.

Our 16 bit support is assembler-only + the terrible hack that is
.code16gcc. Simply using 32 bit registers does the right thing for the
latter.

Fixes PR32681.
------------------------------------------------------------------------

Modified:
    llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/release_40/lib/Target/X86/X86RegisterInfo.td
    llvm/branches/release_40/test/CodeGen/X86/x86-16.ll

Modified: llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp?rev=301437&r1=301436&r2=301437&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp Wed Apr 26 12:52:15 2017
@@ -34722,14 +34722,11 @@ X86TargetLowering::getRegForInlineAsmCon
       if (Subtarget.is64Bit()) {
         Res.first = X86::RAX;
         Res.second = &X86::GR64_ADRegClass;
-      } else if (Subtarget.is32Bit()) {
+      } else {
+        assert((Subtarget.is32Bit() || Subtarget.is16Bit()) &&
+               "Expecting 64, 32 or 16 bit subtarget");
         Res.first = X86::EAX;
         Res.second = &X86::GR32_ADRegClass;
-      } else if (Subtarget.is16Bit()) {
-        Res.first = X86::AX;
-        Res.second = &X86::GR16_ADRegClass;
-      } else {
-        llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
       }
       return Res;
     }

Modified: llvm/branches/release_40/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/X86/X86RegisterInfo.td?rev=301437&r1=301436&r2=301437&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/branches/release_40/lib/Target/X86/X86RegisterInfo.td Wed Apr 26 12:52:15 2017
@@ -438,7 +438,6 @@ def LOW32_ADDR_ACCESS_RBP : RegisterClas
                                           (add LOW32_ADDR_ACCESS, RBP)>;
 
 // A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
-def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
 

Modified: llvm/branches/release_40/test/CodeGen/X86/x86-16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/CodeGen/X86/x86-16.ll?rev=301437&r1=301436&r2=301437&view=diff
==============================================================================
--- llvm/branches/release_40/test/CodeGen/X86/x86-16.ll (original)
+++ llvm/branches/release_40/test/CodeGen/X86/x86-16.ll Wed Apr 26 12:52:15 2017
@@ -12,9 +12,16 @@ define i32 @main() #0 {
 ; CHECK: .code16
 ; CHECK-LABEL: main
 
+define i64 @foo(i32 %index) #0 {
+  %asm = tail call i64 asm "rdmsr", "=A,{cx},~{dirflag},~{fpsr},~{flags}"(i32 %index)
+  ret i64 %asm
+}
+
+; CHECK-LABEL: foo
+; CHECK: rdmsr
 
 attributes #0 = { nounwind }
 
 !llvm.ident = !{!0}
 
-!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}
\ No newline at end of file
+!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}