[llvm-branch-commits] [llvm-branch] r271771 - Merging r268295:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Fri Jun  3 22:43:07 2016
New Revision: 271771

URL: http://llvm.org/viewvc/llvm-project?rev=271771&view=rev
Log:
Merging r268295:

------------------------------------------------------------------------
r268295 | thomas.stellard | 2016-05-02 13:11:44 -0700 (Mon, 02 May 2016) | 7 lines

AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to
scratch

We were using v_readlane_b32 with the lane set to zero, but this won't
work if thread 0 is not active.

Differential Revision: http://reviews.llvm.org/D19745

------------------------------------------------------------------------

Modified:
    llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp
    llvm/branches/release_38/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll

Modified: llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=271771&r1=271770&r2=271771&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Jun  3 22:43:07 2016
@@ -410,9 +410,8 @@ void SIRegisterInfo::eliminateFrameIndex
                   .addImm(i * 4)                          // offset
                   .addMemOperand(MMO);
           BuildMI(*MBB, MI, DL,
-                  TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg)
+                  TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
                   .addReg(TmpReg, RegState::Kill)
-                  .addImm(0)
                   .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
         }
       }

Modified: llvm/branches/release_38/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll?rev=271771&r1=271770&r2=271771&view=diff
==============================================================================
--- llvm/branches/release_38/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll (original)
+++ llvm/branches/release_38/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll Fri Jun  3 22:43:07 2016
@@ -2,6 +2,12 @@
 
 ; Make sure this doesn't crash.
 ; CHECK: {{^}}test:
+; Make sure we are handling hazards correctly.
+; CHECK: buffer_load_dword [[VHI:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:16
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]
+; CHECK-NEXT: s_nop 4
+; CHECK-NEXT: buffer_store_dword v0, s[0:[[HI]]{{\]}}, 0
 ; CHECK: s_endpgm
 define void @test(i32 addrspace(1)* %out, i32 %in) {
   call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()