[llvm-branch-commits] [llvm-branch] r271735 - Merging r266152:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Fri Jun  3 15:48:40 2016
New Revision: 271735

URL: http://llvm.org/viewvc/llvm-project?rev=271735&view=rev
Log:
Merging r266152:

------------------------------------------------------------------------
r266152 | thomas.stellard | 2016-04-12 16:57:30 -0700 (Tue, 12 Apr 2016) | 13 lines

AMDGPU/SI: Fix spilling of 96-bit registers

Summary:
It seems like this was broken in r252327.  I thought we had test cases
for this, but it's really hard to tirgger spills of this exact register
size since they aren't used very much.

Reviewers: arsenm, nhaehnle

Subscribers: nhaehnle, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19021

------------------------------------------------------------------------

Modified:
    llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=271735&r1=271734&r2=271735&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp Fri Jun  3 15:48:40 2016
@@ -525,6 +525,8 @@ static unsigned getVGPRSpillSaveOpcode(u
     return AMDGPU::SI_SPILL_V32_SAVE;
   case 8:
     return AMDGPU::SI_SPILL_V64_SAVE;
+  case 12:
+    return AMDGPU::SI_SPILL_V96_SAVE;
   case 16:
     return AMDGPU::SI_SPILL_V128_SAVE;
   case 32:
@@ -616,6 +618,8 @@ static unsigned getVGPRSpillRestoreOpcod
     return AMDGPU::SI_SPILL_V32_RESTORE;
   case 8:
     return AMDGPU::SI_SPILL_V64_RESTORE;
+  case 12:
+    return AMDGPU::SI_SPILL_V96_RESTORE;
   case 16:
     return AMDGPU::SI_SPILL_V128_RESTORE;
   case 32: