[llvm-branch-commits] [llvm-branch] r271721 - Merging r262728:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Fri Jun  3 15:22:42 2016
New Revision: 271721

URL: http://llvm.org/viewvc/llvm-project?rev=271721&view=rev
Log:
Merging r262728:

------------------------------------------------------------------------
r262728 | thomas.stellard | 2016-03-04 10:02:01 -0800 (Fri, 04 Mar 2016) | 19 lines

AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserter

Summary:
This allows us to use virtual registers when we need extra registers
for inserting spill instructions in SIRegisterInfo:eliminateFrameIndex().

Once all the frame indices have been eliminated, the
PrologEpilogueInserter does an extra pass over the program to replace
all virtual registers with physical ones.

This allows us to make more efficient use of our emergency spill slots,
so we only need to create one.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D17591

------------------------------------------------------------------------

Modified:
    llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp
    llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.h

Modified: llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=271721&r1=271720&r2=271721&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Jun  3 15:22:42 2016
@@ -182,6 +182,11 @@ bool SIRegisterInfo::requiresRegisterSca
   return Fn.getFrameInfo()->hasStackObjects();
 }
 
+bool
+SIRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
+  return MF.getFrameInfo()->hasStackObjects();
+}
+
 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
 
   switch (Op) {
@@ -222,11 +227,11 @@ void SIRegisterInfo::buildScratchLoadSto
                                            unsigned Value,
                                            unsigned ScratchRsrcReg,
                                            unsigned ScratchOffset,
-                                           int64_t Offset,
-                                           RegScavenger *RS) const {
+                                           int64_t Offset) const {
 
   MachineBasicBlock *MBB = MI->getParent();
-  const MachineFunction *MF = MI->getParent()->getParent();
+  MachineFunction *MF = MI->getParent()->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
   const SIInstrInfo *TII =
       static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
   LLVMContext &Ctx = MF->getFunction()->getContext();
@@ -241,7 +246,7 @@ void SIRegisterInfo::buildScratchLoadSto
   unsigned Size = NumSubRegs * 4;
 
   if (!isUInt<12>(Offset + Size)) {
-    SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
+    SOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
     if (SOffset == AMDGPU::NoRegister) {
       RanOutOfSGPRs = true;
       SOffset = AMDGPU::SGPR0;
@@ -283,6 +288,7 @@ void SIRegisterInfo::eliminateFrameIndex
                                         int SPAdj, unsigned FIOperandNum,
                                         RegScavenger *RS) const {
   MachineFunction *MF = MI->getParent()->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
   MachineBasicBlock *MBB = MI->getParent();
   SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
   MachineFrameInfo *FrameInfo = MF->getFrameInfo();
@@ -375,7 +381,7 @@ void SIRegisterInfo::eliminateFrameIndex
             TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
             TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
             TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
-             FrameInfo->getObjectOffset(Index), RS);
+             FrameInfo->getObjectOffset(Index));
       MI->eraseFromParent();
       break;
     case AMDGPU::SI_SPILL_V32_RESTORE:
@@ -388,7 +394,7 @@ void SIRegisterInfo::eliminateFrameIndex
             TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
             TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
             TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
-            FrameInfo->getObjectOffset(Index), RS);
+            FrameInfo->getObjectOffset(Index));
       MI->eraseFromParent();
       break;
     }
@@ -397,7 +403,7 @@ void SIRegisterInfo::eliminateFrameIndex
       int64_t Offset = FrameInfo->getObjectOffset(Index);
       FIOp.ChangeToImmediate(Offset);
       if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
-        unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
+        unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
         BuildMI(*MBB, MI, MI->getDebugLoc(),
                 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
                 .addImm(Offset);

Modified: llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.h?rev=271721&r1=271720&r2=271721&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.h (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.h Fri Jun  3 15:22:42 2016
@@ -49,6 +49,8 @@ public:
 
   bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
 
+  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
+
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS) const override;
@@ -162,7 +164,7 @@ private:
   void buildScratchLoadStore(MachineBasicBlock::iterator MI,
                              unsigned LoadStoreOp, unsigned Value,
                              unsigned ScratchRsrcReg, unsigned ScratchOffset,
-                             int64_t Offset, RegScavenger *RS) const;
+                             int64_t Offset) const;
 };
 
 } // End namespace llvm