[llvm-branch-commits] [llvm-branch] r271641 - Merging r260588:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Fri Jun  3 04:50:09 2016
New Revision: 271641

URL: http://llvm.org/viewvc/llvm-project?rev=271641&view=rev
Log:
Merging r260588:

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r260588 | thomas.stellard | 2016-02-11 13:14:34 -0800 (Thu, 11 Feb 2016) | 20 lines

AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklist

Summary:
When we split SMRD instructions into two MUBUFs we were adding the users
of the newly created MUBUFs to the VALU worklist.  However, the only
users these instructions had was the REG_SEQUENCE that was inserted
by splitSMRD when the original SMRD instruction was split.

We need to make sure to add the users of the original SMRD to the VALU
worklist before it is split.

I have a test case, but it requires one other bug fix, so it will be
added in a later commt.

Reviewers: mareko, arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D17101

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Modified:
    llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=271641&r1=271640&r2=271641&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/SIInstrInfo.cpp Fri Jun  3 04:50:09 2016
@@ -2430,6 +2430,7 @@ void SIInstrInfo::moveSMRDToVALU(Machine
     }
     case 32: {
       MachineInstr *Lo, *Hi;
+      addUsersToMoveToVALUWorklist(MI->getOperand(0).getReg(), MRI, Worklist);
       splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
                 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
       MI->eraseFromParent();
@@ -2440,6 +2441,7 @@ void SIInstrInfo::moveSMRDToVALU(Machine
 
     case 64: {
       MachineInstr *Lo, *Hi;
+      addUsersToMoveToVALUWorklist(MI->getOperand(0).getReg(), MRI, Worklist);
       splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
                 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
       MI->eraseFromParent();