[llvm-branch-commits] [llvm-branch] r271590 - Merging r259059:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Thu Jun  2 16:01:41 2016
New Revision: 271590

URL: http://llvm.org/viewvc/llvm-project?rev=271590&view=rev
Log:
Merging r259059:

------------------------------------------------------------------------
r259059 | thomas.stellard | 2016-01-28 09:13:44 -0800 (Thu, 28 Jan 2016) | 14 lines

AMDGPU: waitcnt operand fixes

Summary:
Allow lgkmcnt up to 0xF (hardware allows that).
Fix mask for ExpCnt in AMDGPUInstPrinter.

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16314

Patch by: Nikolay Haustov

------------------------------------------------------------------------

Modified:
    llvm/branches/release_38/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    llvm/branches/release_38/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
    llvm/branches/release_38/lib/Target/AMDGPU/SIInsertWaits.cpp
    llvm/branches/release_38/test/MC/AMDGPU/sopp.s

Modified: llvm/branches/release_38/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=271590&r1=271589&r2=271590&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Thu Jun  2 16:01:41 2016
@@ -1516,7 +1516,7 @@ bool AMDGPUAsmParser::parseCnt(int64_t &
     CntMask = 0x7;
     CntShift = 4;
   } else if (CntName == "lgkmcnt") {
-    CntMask = 0x7;
+    CntMask = 0xf;
     CntShift = 8;
   } else {
     return true;
@@ -1532,8 +1532,8 @@ AMDGPUAsmParser::parseSWaitCntOps(Operan
   // Disable all counters by default.
   // vmcnt   [3:0]
   // expcnt  [6:4]
-  // lgkmcnt [10:8]
-  int64_t CntVal = 0x77f;
+  // lgkmcnt [11:8]
+  int64_t CntVal = 0xf7f;
   SMLoc S = Parser.getTok().getLoc();
 
   switch(getLexer().getKind()) {

Modified: llvm/branches/release_38/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=271590&r1=271589&r2=271590&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Thu Jun  2 16:01:41 2016
@@ -616,12 +616,9 @@ void AMDGPUInstPrinter::printSendMsg(con
 
 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
                                       raw_ostream &O) {
-  // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
-  // SIInsertWaits.cpp bits usage does not match ISA docs description but it
-  // works so it might be a misprint in docs.
   unsigned SImm16 = MI->getOperand(OpNo).getImm();
   unsigned Vmcnt = SImm16 & 0xF;
-  unsigned Expcnt = (SImm16 >> 4) & 0xF;
+  unsigned Expcnt = (SImm16 >> 4) & 0x7;
   unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
 
   bool NeedSpace = false;
@@ -638,7 +635,7 @@ void AMDGPUInstPrinter::printWaitFlag(co
     NeedSpace = true;
   }
 
-  if (Lgkmcnt != 0x7) {
+  if (Lgkmcnt != 0xF) {
     if (NeedSpace)
       O << ' ';
     O << "lgkmcnt(" << Lgkmcnt << ')';

Modified: llvm/branches/release_38/lib/Target/AMDGPU/SIInsertWaits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/SIInsertWaits.cpp?rev=271590&r1=271589&r2=271590&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/SIInsertWaits.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/SIInsertWaits.cpp Thu Jun  2 16:01:41 2016
@@ -138,7 +138,7 @@ public:
 
 char SIInsertWaits::ID = 0;
 
-const Counters SIInsertWaits::WaitCounts = { { 15, 7, 7 } };
+const Counters SIInsertWaits::WaitCounts = { { 15, 7, 15 } };
 const Counters SIInsertWaits::ZeroCounts = { { 0, 0, 0 } };
 
 FunctionPass *llvm::createSIInsertWaits(TargetMachine &tm) {
@@ -379,7 +379,7 @@ bool SIInsertWaits::insertWait(MachineBa
   BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
           .addImm((Counts.Named.VM & 0xF) |
                   ((Counts.Named.EXP & 0x7) << 4) |
-                  ((Counts.Named.LGKM & 0x7) << 8));
+                  ((Counts.Named.LGKM & 0xF) << 8));
 
   LastOpcodeType = OTHER;
   LastInstWritesM0 = false;

Modified: llvm/branches/release_38/test/MC/AMDGPU/sopp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/MC/AMDGPU/sopp.s?rev=271590&r1=271589&r2=271590&view=diff
==============================================================================
--- llvm/branches/release_38/test/MC/AMDGPU/sopp.s (original)
+++ llvm/branches/release_38/test/MC/AMDGPU/sopp.s Thu Jun  2 16:01:41 2016
@@ -40,16 +40,22 @@ s_nop 0xffff  // CHECK: s_nop 0xffff ; e
   // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 
   s_waitcnt vmcnt(1)
-  // CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x07,0x8c,0xbf]
+  // CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x0f,0x8c,0xbf]
+
+  s_waitcnt vmcnt(9)
+  // CHECK: s_waitcnt vmcnt(9) ; encoding: [0x79,0x0f,0x8c,0xbf]
 
   s_waitcnt expcnt(2)
-  // CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x07,0x8c,0xbf]
+  // CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x0f,0x8c,0xbf]
 
   s_waitcnt lgkmcnt(3)
   // CHECK: s_waitcnt lgkmcnt(3) ; encoding: [0x7f,0x03,0x8c,0xbf]
 
+  s_waitcnt lgkmcnt(9)
+  // CHECK: s_waitcnt lgkmcnt(9) ; encoding: [0x7f,0x09,0x8c,0xbf]
+
   s_waitcnt vmcnt(0), expcnt(0)
-  // CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x07,0x8c,0xbf]
+  // CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x0f,0x8c,0xbf]
 
 
   s_sethalt 9        // CHECK: s_sethalt 9 ; encoding: [0x09,0x00,0x8d,0xbf]