[llvm-branch-commits] [llvm-branch] r277084 - Merging r276980:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Thu Jul 28 18:31:17 2016
New Revision: 277084

URL: http://llvm.org/viewvc/llvm-project?rev=277084&view=rev
Log:
Merging r276980:
------------------------------------------------------------------------
r276980 | tstellar | 2016-07-28 07:30:43 -0700 (Thu, 28 Jul 2016) | 12 lines

AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling

Summary:
We were using reserved VGPRs for SGPR spilling and this was causing
some programs with a workgroup size of 1024 to use more than 64
registers, which is illegal.

Reviewers: arsenm, mareko, nhaehnle

Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22032
------------------------------------------------------------------------

Modified:
    llvm/branches/release_39/   (props changed)
    llvm/branches/release_39/lib/Target/AMDGPU/SIInstrInfo.cpp
    llvm/branches/release_39/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.cpp
    llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.h

Propchange: llvm/branches/release_39/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Jul 28 18:31:17 2016
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276740,276956
+/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276740,276956,276980

Modified: llvm/branches/release_39/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=277084&r1=277083&r2=277084&view=diff
==============================================================================
--- llvm/branches/release_39/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/branches/release_39/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Jul 28 18:31:17 2016
@@ -738,7 +738,8 @@ unsigned SIInstrInfo::calculateLDSSpillA
     MachineBasicBlock::iterator Insert = Entry.front();
     DebugLoc DL = Insert->getDebugLoc();
 
-    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
+    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
+                                   *MF);
     if (TIDReg == AMDGPU::NoRegister)
       return TIDReg;
 

Modified: llvm/branches/release_39/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=277084&r1=277083&r2=277084&view=diff
==============================================================================
--- llvm/branches/release_39/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (original)
+++ llvm/branches/release_39/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Thu Jul 28 18:31:17 2016
@@ -203,7 +203,8 @@ SIMachineFunctionInfo::SpilledReg SIMach
   Spill.Lane = Lane;
 
   if (!LaneVGPRs.count(LaneVGPRIdx)) {
-    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
+    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,
+                                                *MF);
 
     if (LaneVGPR == AMDGPU::NoRegister)
       // We have no VGPRs left for spilling SGPRs.

Modified: llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=277084&r1=277083&r2=277084&view=diff
==============================================================================
--- llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.cpp Thu Jul 28 18:31:17 2016
@@ -957,10 +957,13 @@ unsigned SIRegisterInfo::getPreloadedVal
 /// \brief Returns a register that is not used at any point in the function.
 ///        If all registers are used, then this function will return
 //         AMDGPU::NoRegister.
-unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
-                                           const TargetRegisterClass *RC) const {
+unsigned
+SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
+                                   const TargetRegisterClass *RC,
+                                   const MachineFunction &MF) const {
+
   for (unsigned Reg : *RC)
-    if (!MRI.isPhysRegUsed(Reg))
+    if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg))
       return Reg;
   return AMDGPU::NoRegister;
 }

Modified: llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.h?rev=277084&r1=277083&r2=277084&view=diff
==============================================================================
--- llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.h (original)
+++ llvm/branches/release_39/lib/Target/AMDGPU/SIRegisterInfo.h Thu Jul 28 18:31:17 2016
@@ -185,7 +185,8 @@ public:
   unsigned getNumSGPRsAllowed(const SISubtarget &ST, unsigned WaveCount) const;
 
   unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
-                              const TargetRegisterClass *RC) const;
+                              const TargetRegisterClass *RC,
+                              const MachineFunction &MF) const;
 
   unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
   unsigned getVGPR32PressureSet() const { return VGPR32SetID; };