[llvm-branch-commits] [llvm-branch] r260687 - Merging r260427:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Fri Feb 12 10:18:07 2016
New Revision: 260687

URL: http://llvm.org/viewvc/llvm-project?rev=260687&view=rev
Log:
Merging r260427:
------------------------------------------------------------------------
r260427 | nha | 2016-02-10 12:13:58 -0800 (Wed, 10 Feb 2016) | 16 lines

AMDGPU: Release the scavenged offset register during VGPR spill

Summary:
This fixes a crash where subsequent spills would be unable to scavenge
a register. In particular, it fixes a crash in piglit's
spec at glsl-1.50@execution at geometry@max-input-components (the test still
has a shader that fails to compile because of too many SGPR spills, but
at least it doesn't crash any more).

This is a candidate for the release branch.

Reviewers: arsenm, tstellarAMD

Subscribers: qcolombet, arsenm

Differential Revision: http://reviews.llvm.org/D16558
------------------------------------------------------------------------

Added:
    llvm/branches/release_38/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
      - copied unchanged from r260427, llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
Modified:
    llvm/branches/release_38/   (props changed)
    llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp

Propchange: llvm/branches/release_38/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Feb 12 10:18:07 2016
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259740,259798,259835,259840,259886,259888,259958,260587
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259740,259798,259835,259840,259886,259888,259958,260427,260587

Modified: llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=260687&r1=260686&r2=260687&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Feb 12 10:18:07 2016
@@ -234,6 +234,7 @@ void SIRegisterInfo::buildScratchLoadSto
   bool IsLoad = TII->get(LoadStoreOp).mayLoad();
 
   bool RanOutOfSGPRs = false;
+  bool Scavenged = false;
   unsigned SOffset = ScratchOffset;
 
   unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
@@ -244,6 +245,8 @@ void SIRegisterInfo::buildScratchLoadSto
     if (SOffset == AMDGPU::NoRegister) {
       RanOutOfSGPRs = true;
       SOffset = AMDGPU::SGPR0;
+    } else {
+      Scavenged = true;
     }
     BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
             .addReg(ScratchOffset)
@@ -259,10 +262,14 @@ void SIRegisterInfo::buildScratchLoadSto
         getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
         Value;
 
+    unsigned SOffsetRegState = 0;
+    if (i + 1 == e && Scavenged)
+      SOffsetRegState |= RegState::Kill;
+
     BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
       .addReg(SubReg, getDefRegState(IsLoad))
       .addReg(ScratchRsrcReg)
-      .addReg(SOffset)
+      .addReg(SOffset, SOffsetRegState)
       .addImm(Offset)
       .addImm(0) // glc
       .addImm(0) // slc