[llvm-branch-commits] [llvm-branch] r278239 - Merging r278002:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Wed Aug 10 11:27:26 2016
New Revision: 278239

URL: http://llvm.org/viewvc/llvm-project?rev=278239&view=rev
Log:
Merging r278002:
------------------------------------------------------------------------
r278002 | sbaranga | 2016-08-08 06:13:57 -0700 (Mon, 08 Aug 2016) | 18 lines

[AArch64] PR28877: Don't assume we're running after legalization when creating vcvtfp2fxs

Summary:
The DAG combine transformation that was generating the
aarch64_neon_vcvtfp2fxs node was assuming that all
inputs where legal and wasn't accounting that the input
could be a v4f64 if we're trying to do the transformation
before legalization. We now bail out in this case.

All illegal types besides v4f64 were already rejected.

Fixes https://llvm.org/bugs/show_bug.cgi?id=28877.

Reviewers: jmolloy

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: https://reviews.llvm.org/D23261
------------------------------------------------------------------------

Added:
    llvm/branches/release_39/test/CodeGen/AArch64/aarch64-vcvtfp2fxs-combine.ll
      - copied unchanged from r278002, llvm/trunk/test/CodeGen/AArch64/aarch64-vcvtfp2fxs-combine.ll
Modified:
    llvm/branches/release_39/   (props changed)
    llvm/branches/release_39/lib/Target/AArch64/AArch64ISelLowering.cpp

Propchange: llvm/branches/release_39/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Aug 10 11:27:26 2016
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276740,276956,276980,277114,277135,277371,277500,277504,277625,277691,277693,277773,278086,278133
+/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276740,276956,276980,277114,277135,277371,277500,277504,277625,277691,277693,277773,278002,278086,278133

Modified: llvm/branches/release_39/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=278239&r1=278238&r2=278239&view=diff
==============================================================================
--- llvm/branches/release_39/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/branches/release_39/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Aug 10 11:27:26 2016
@@ -7685,6 +7685,7 @@ static SDValue performIntToFpCombine(SDN
 /// Fold a floating-point multiply by power of two into floating-point to
 /// fixed-point conversion.
 static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
+                                     TargetLowering::DAGCombinerInfo &DCI,
                                      const AArch64Subtarget *Subtarget) {
   if (!Subtarget->hasNEON())
     return SDValue();
@@ -7728,10 +7729,16 @@ static SDValue performFpToIntCombine(SDN
     ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
     break;
   case 4:
-    ResTy = MVT::v4i32;
+    ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64;
     break;
   }
 
+  if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
+    return SDValue();
+
+  assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) &&
+         "Illegal vector type after legalization");
+
   SDLoc DL(N);
   bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
   unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfp2fxs
@@ -9853,7 +9860,7 @@ SDValue AArch64TargetLowering::PerformDA
     return performIntToFpCombine(N, DAG, Subtarget);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
-    return performFpToIntCombine(N, DAG, Subtarget);
+    return performFpToIntCombine(N, DAG, DCI, Subtarget);
   case ISD::FDIV:
     return performFDivCombine(N, DAG, Subtarget);
   case ISD::OR: