[llvm-branch-commits] [lldb] r278047 - Merging r277426:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Aug 8 13:20:15 PDT 2016
Author: hans
Date: Mon Aug 8 15:20:15 2016
New Revision: 278047
URL: http://llvm.org/viewvc/llvm-project?rev=278047&view=rev
Log:
Merging r277426:
------------------------------------------------------------------------
r277426 | nitesh.jain | 2016-08-02 00:18:07 -0700 (Tue, 02 Aug 2016) | 7 lines
[LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix emulation for (D)ADDIU, SD/SW and LW/LD instructions
Reviewers: clayborg, jaydeep, bhushan
Subscribers: mohit.bhakkad, slthakur, sdardis, lldb-commits
Differential Revision: https://reviews.llvm.org/D20357
------------------------------------------------------------------------
Modified:
lldb/branches/release_39/ (props changed)
lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
Propchange: lldb/branches/release_39/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Aug 8 15:20:15 2016
@@ -1,3 +1,3 @@
/lldb/branches/apple/python-GIL:156467-162159
/lldb/branches/iohandler:198360-200250
-/lldb/trunk:277343
+/lldb/trunk:277343,277426
Modified: lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp?rev=278047&r1=278046&r2=278047&view=diff
==============================================================================
--- lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp (original)
+++ lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Mon Aug 8 15:20:15 2016
@@ -494,9 +494,13 @@ EmulateInstructionMIPS::GetOpcodeForInst
//----------------------------------------------------------------------
// Prologue/Epilogue instructions
//----------------------------------------------------------------------
- { "ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu, "ADDIU rt,rs,immediate" },
- { "SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt,offset(rs)" },
- { "LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt,offset(base)" },
+ { "ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu, "ADDIU rt, rs, immediate" },
+ { "SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt, offset(rs)" },
+ { "LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt, offset(base)" },
+ { "SUBU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "SUBU rd, rs, rt" },
+ { "ADDU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "ADDU rd, rs, rt" },
+ { "LUI", &EmulateInstructionMIPS::Emulate_LUI, "LUI rt, immediate" },
+
//----------------------------------------------------------------------
// MicroMIPS Prologue/Epilogue instructions
//----------------------------------------------------------------------
@@ -904,36 +908,57 @@ EmulateInstructionMIPS::nonvolatile_reg_
bool
EmulateInstructionMIPS::Emulate_ADDiu (llvm::MCInst& insn)
{
+ // ADDIU rt, rs, immediate
+ // GPR[rt] <- GPR[rs] + sign_extend(immediate)
+
+ uint8_t dst, src;
bool success = false;
const uint32_t imm16 = insn.getOperand(2).getImm();
- uint32_t imm = SignedBits(imm16, 15, 0);
- uint64_t result;
- uint32_t src, dst;
+ int64_t imm = SignedBits(imm16, 15, 0);
dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
- /* Check if this is addiu sp,<src>,imm16 */
- if (dst == dwarf_sp_mips)
+ // If immediate value is greater then 2^16 - 1 then clang generate
+ // LUI, ADDIU, SUBU instructions in prolog.
+ // Example
+ // lui $1, 0x2
+ // addiu $1, $1, -0x5920
+ // subu $sp, $sp, $1
+ // In this case, ADDIU dst and src will be same and not equal to sp
+ if (dst == src)
{
+ Context context;
+
/* read <src> register */
- uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success);
+ const int64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success);
if (!success)
return false;
- result = src_opd_val + imm;
+ /* Check if this is daddiu sp, sp, imm16 */
+ if (dst == dwarf_sp_mips)
+ {
+ uint64_t result = src_opd_val + imm;
+ RegisterInfo reg_info_sp;
- Context context;
- RegisterInfo reg_info_sp;
- if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
- context.SetRegisterPlusOffset (reg_info_sp, imm);
+ if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
+ context.SetRegisterPlusOffset (reg_info_sp, imm);
- /* We are allocating bytes on stack */
- context.type = eContextAdjustStackPointer;
+ /* We are allocating bytes on stack */
+ context.type = eContextAdjustStackPointer;
- WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result);
+ WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result);
+ return true;
+ }
+
+ imm += src_opd_val;
+ context.SetImmediateSigned (imm);
+ context.type = eContextImmediate;
+
+ if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + dst, imm))
+ return false;
}
-
+
return true;
}
@@ -968,7 +993,7 @@ EmulateInstructionMIPS::Emulate_SW (llvm
WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address);
/* We look for sp based non-volatile register stores */
- if (base == dwarf_sp_mips && nonvolatile_reg_p (src))
+ if (nonvolatile_reg_p (src))
{
RegisterInfo reg_info_src;
@@ -1027,7 +1052,7 @@ EmulateInstructionMIPS::Emulate_LW (llvm
bad_vaddr_context.type = eContextInvalid;
WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address);
- if (base == dwarf_sp_mips && nonvolatile_reg_p (src))
+ if (nonvolatile_reg_p (src))
{
RegisterValue data_src;
RegisterInfo reg_info_src;
@@ -1047,6 +1072,105 @@ EmulateInstructionMIPS::Emulate_LW (llvm
return false;
}
+
+bool
+EmulateInstructionMIPS::Emulate_SUBU_ADDU (llvm::MCInst& insn)
+{
+ // SUBU sp, <src>, <rt>
+ // ADDU sp, <src>, <rt>
+ // ADDU dst, sp, <rt>
+
+ bool success = false;
+ uint64_t result;
+ uint8_t src, dst, rt;
+ const char *op_name = m_insn_info->getName (insn.getOpcode ());
+
+ dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+ src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
+
+ /* Check if sp is destination register */
+ if (dst == dwarf_sp_mips)
+ {
+ rt = m_reg_info->getEncodingValue (insn.getOperand(2).getReg());
+
+ /* read <src> register */
+ uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success);
+ if (!success)
+ return false;
+
+ /* read <rt > register */
+ uint64_t rt_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success);
+ if (!success)
+ return false;
+
+ if (!strcasecmp (op_name, "SUBU"))
+ result = src_opd_val - rt_opd_val;
+ else
+ result = src_opd_val + rt_opd_val;
+
+ Context context;
+ RegisterInfo reg_info_sp;
+ if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
+ context.SetRegisterPlusOffset (reg_info_sp, rt_opd_val);
+
+ /* We are allocating bytes on stack */
+ context.type = eContextAdjustStackPointer;
+
+ WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result);
+
+ return true;
+ }
+ else if (src == dwarf_sp_mips)
+ {
+ rt = m_reg_info->getEncodingValue (insn.getOperand(2).getReg());
+
+ /* read <src> register */
+ uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success);
+ if (!success)
+ return false;
+
+ /* read <rt> register */
+ uint64_t rt_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success);
+ if (!success)
+ return false;
+
+ Context context;
+
+ if (!strcasecmp (op_name, "SUBU"))
+ result = src_opd_val - rt_opd_val;
+ else
+ result = src_opd_val + rt_opd_val;
+
+ context.SetImmediateSigned (result);
+ context.type = eContextImmediate;
+
+ if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + dst, result))
+ return false;
+ }
+
+ return true;
+}
+
+bool
+EmulateInstructionMIPS::Emulate_LUI (llvm::MCInst& insn)
+{
+ // LUI rt, immediate
+ // GPR[rt] <- sign_extend(immediate << 16)
+
+ const uint32_t imm32 = insn.getOperand(1).getImm() << 16;
+ int64_t imm = SignedBits(imm32, 31, 0);
+ uint8_t rt;
+ Context context;
+
+ rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+ context.SetImmediateSigned (imm);
+ context.type = eContextImmediate;
+
+ if (WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + rt, imm))
+ return true;
+
+ return false;
+}
bool
EmulateInstructionMIPS::Emulate_ADDIUSP (llvm::MCInst& insn)
Modified: lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
URL: http://llvm.org/viewvc/llvm-project/lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h?rev=278047&r1=278046&r2=278047&view=diff
==============================================================================
--- lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h (original)
+++ lldb/branches/release_39/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h Mon Aug 8 15:20:15 2016
@@ -127,6 +127,12 @@ protected:
Emulate_ADDiu (llvm::MCInst& insn);
bool
+ Emulate_SUBU_ADDU (llvm::MCInst& insn);
+
+ bool
+ Emulate_LUI (llvm::MCInst& insn);
+
+ bool
Emulate_SW (llvm::MCInst& insn);
bool
Modified: lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp?rev=278047&r1=278046&r2=278047&view=diff
==============================================================================
--- lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp (original)
+++ lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp Mon Aug 8 15:20:15 2016
@@ -482,10 +482,15 @@ EmulateInstructionMIPS64::GetOpcodeForIn
//----------------------------------------------------------------------
// Prologue/Epilogue instructions
//----------------------------------------------------------------------
- { "DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, "DADDIU rt,rs,immediate" },
- { "ADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, "ADDIU rt,rs,immediate" },
- { "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" },
- { "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)" },
+ { "DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, "DADDIU rt, rs, immediate" },
+ { "ADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, "ADDIU rt, rs, immediate" },
+ { "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt, offset(rs)" },
+ { "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt, offset(base)" },
+ { "DSUBU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU, "DSUBU rd, rs, rt" },
+ { "SUBU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU, "SUBU rd, rs, rt" },
+ { "DADDU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU, "DADDU rd, rs, rt" },
+ { "ADDU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU, "ADDU rd, rs, rt" },
+ { "LUI", &EmulateInstructionMIPS64::Emulate_LUI, "LUI rt, immediate" },
@@ -771,36 +776,57 @@ EmulateInstructionMIPS64::nonvolatile_re
bool
EmulateInstructionMIPS64::Emulate_DADDiu (llvm::MCInst& insn)
{
+ // DADDIU rt, rs, immediate
+ // GPR[rt] <- GPR[rs] + sign_extend(immediate)
+
+ uint8_t dst, src;
bool success = false;
const uint32_t imm16 = insn.getOperand(2).getImm();
- uint64_t imm = SignedBits(imm16, 15, 0);
- uint64_t result;
- uint32_t src, dst;
+ int64_t imm = SignedBits(imm16, 15, 0);
dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
- /* Check if this is daddiu sp,<src>,imm16 */
- if (dst == dwarf_sp_mips64)
+ // If immediate is greater than 2^16 - 1 then clang generate
+ // LUI, (D)ADDIU,(D)SUBU instructions in prolog.
+ // Example
+ // lui $1, 0x2
+ // daddiu $1, $1, -0x5920
+ // dsubu $sp, $sp, $1
+ // In this case, (D)ADDIU dst and src will be same and not equal to sp
+ if (dst == src)
{
+ Context context;
+
/* read <src> register */
- uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success);
+ const int64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success);
if (!success)
return false;
- result = src_opd_val + imm;
+ /* Check if this is daddiu sp, sp, imm16 */
+ if (dst == dwarf_sp_mips64)
+ {
+ uint64_t result = src_opd_val + imm;
+ RegisterInfo reg_info_sp;
- Context context;
- RegisterInfo reg_info_sp;
- if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
- context.SetRegisterPlusOffset (reg_info_sp, imm);
+ if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
+ context.SetRegisterPlusOffset (reg_info_sp, imm);
- /* We are allocating bytes on stack */
- context.type = eContextAdjustStackPointer;
+ /* We are allocating bytes on stack */
+ context.type = eContextAdjustStackPointer;
- WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips64, result);
+ WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips64, result);
+ return true;
+ }
+
+ imm += src_opd_val;
+ context.SetImmediateSigned (imm);
+ context.type = eContextImmediate;
+
+ if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips64 + dst, imm))
+ return false;
}
-
+
return true;
}
@@ -832,7 +858,7 @@ EmulateInstructionMIPS64::Emulate_SD (ll
address = address + imm;
/* We look for sp based non-volatile register stores */
- if (base == dwarf_sp_mips64 && nonvolatile_reg_p (src))
+ if (nonvolatile_reg_p (src))
{
Context context;
RegisterValue data_src;
@@ -888,7 +914,7 @@ EmulateInstructionMIPS64::Emulate_LD (ll
WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64, address);
- if (base == dwarf_sp_mips64 && nonvolatile_reg_p (src))
+ if (nonvolatile_reg_p (src))
{
RegisterValue data_src;
RegisterInfo reg_info_src;
@@ -908,6 +934,104 @@ EmulateInstructionMIPS64::Emulate_LD (ll
return false;
}
+bool
+EmulateInstructionMIPS64::Emulate_LUI (llvm::MCInst& insn)
+{
+ // LUI rt, immediate
+ // GPR[rt] <- sign_extend(immediate << 16)
+
+ const uint32_t imm32 = insn.getOperand(1).getImm() << 16;
+ int64_t imm = SignedBits(imm32, 31, 0);
+ uint8_t rt;
+ Context context;
+
+ rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+ context.SetImmediateSigned (imm);
+ context.type = eContextImmediate;
+
+ if (WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips64 + rt, imm))
+ return true;
+
+ return false;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_DSUBU_DADDU (llvm::MCInst& insn)
+{
+ // DSUBU sp, <src>, <rt>
+ // DADDU sp, <src>, <rt>
+ // DADDU dst, sp, <rt>
+
+ bool success = false;
+ uint64_t result;
+ uint8_t src, dst, rt;
+ const char *op_name = m_insn_info->getName (insn.getOpcode ());
+
+ dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+ src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
+
+ /* Check if sp is destination register */
+ if (dst == dwarf_sp_mips64)
+ {
+ rt = m_reg_info->getEncodingValue (insn.getOperand(2).getReg());
+
+ /* read <src> register */
+ uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success);
+ if (!success)
+ return false;
+
+ /* read <rt > register */
+ uint64_t rt_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
+ if (!success)
+ return false;
+
+ if (!strcasecmp (op_name, "DSUBU") || !strcasecmp (op_name, "SUBU"))
+ result = src_opd_val - rt_opd_val;
+ else
+ result = src_opd_val + rt_opd_val;
+
+ Context context;
+ RegisterInfo reg_info_sp;
+ if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
+ context.SetRegisterPlusOffset (reg_info_sp, rt_opd_val);
+
+ /* We are allocating bytes on stack */
+ context.type = eContextAdjustStackPointer;
+
+ WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips64, result);
+
+ return true;
+ }
+ else if (src == dwarf_sp_mips64)
+ {
+ rt = m_reg_info->getEncodingValue (insn.getOperand(2).getReg());
+
+ /* read <src> register */
+ uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success);
+ if (!success)
+ return false;
+
+ /* read <rt> register */
+ uint64_t rt_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
+ if (!success)
+ return false;
+
+ Context context;
+
+ if (!strcasecmp (op_name, "DSUBU") || !strcasecmp (op_name, "SUBU"))
+ result = src_opd_val - rt_opd_val;
+ else
+ result = src_opd_val + rt_opd_val;
+
+ context.SetImmediateSigned (result);
+ context.type = eContextImmediate;
+
+ if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips64 + dst, result))
+ return false;
+ }
+
+ return true;
+}
/*
Emulate below MIPS branch instructions.
Modified: lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
URL: http://llvm.org/viewvc/llvm-project/lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h?rev=278047&r1=278046&r2=278047&view=diff
==============================================================================
--- lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h (original)
+++ lldb/branches/release_39/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h Mon Aug 8 15:20:15 2016
@@ -121,6 +121,12 @@ protected:
Emulate_DADDiu (llvm::MCInst& insn);
bool
+ Emulate_DSUBU_DADDU (llvm::MCInst& insn);
+
+ bool
+ Emulate_LUI (llvm::MCInst& insn);
+
+ bool
Emulate_SD (llvm::MCInst& insn);
bool
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