[llvm-branch-commits] [llvm-branch] r253230 - Merging r243661:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Mon Nov 16 11:23:23 2015
New Revision: 253230

URL: http://llvm.org/viewvc/llvm-project?rev=253230&view=rev
Log:
Merging r243661:

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r243661 | Matthew.Arsenault | 2015-07-30 13:03:11 -0400 (Thu, 30 Jul 2015) | 6 lines

AMDGPU: Set SubRegIndex size and offset

I'm not sure what reasons the comment here could have
had for not setting these. Without these set, there is
an assertion hit during DWARF emission.

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Modified:
    llvm/branches/release_37/lib/Target/AMDGPU/AMDGPURegisterInfo.td

Modified: llvm/branches/release_37/lib/Target/AMDGPU/AMDGPURegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/AMDGPURegisterInfo.td?rev=253230&r1=253229&r2=253230&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AMDGPU/AMDGPURegisterInfo.td (original)
+++ llvm/branches/release_37/lib/Target/AMDGPU/AMDGPURegisterInfo.td Mon Nov 16 11:23:23 2015
@@ -14,8 +14,7 @@
 let Namespace = "AMDGPU" in {
 
 foreach Index = 0-15 in {
-  // Indices are used in a variety of ways here, so don't set a size/offset.
-  def sub#Index : SubRegIndex<-1, -1>;
+  def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
 def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;