[llvm-branch-commits] [llvm-branch] r252476 - Merging r245907:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Mon Nov  9 10:24:59 2015
New Revision: 252476

URL: http://llvm.org/viewvc/llvm-project?rev=252476&view=rev
Log:
Merging r245907:

------------------------------------------------------------------------
r245907 | hfinkel | 2015-08-24 19:48:28 -0400 (Mon, 24 Aug 2015) | 6 lines

[PowerPC] PPCVSXFMAMutate should ignore trivial-copy addends

We might end up with a trivial copy as the addend, and if so, we should ignore
the corresponding FMA instruction. The trivial copy can be coalesced away later,
so there's nothing to do here. We should not, however, assert. Fixes PR24544.

------------------------------------------------------------------------

Added:
    llvm/branches/release_37/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll
Modified:
    llvm/branches/release_37/lib/Target/PowerPC/PPCVSXFMAMutate.cpp

Modified: llvm/branches/release_37/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/PowerPC/PPCVSXFMAMutate.cpp?rev=252476&r1=252475&r2=252476&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/PowerPC/PPCVSXFMAMutate.cpp (original)
+++ llvm/branches/release_37/lib/Target/PowerPC/PPCVSXFMAMutate.cpp Mon Nov  9 10:24:59 2015
@@ -186,11 +186,14 @@ protected:
         if (!KilledProdOp)
           continue;
 
-        // For virtual registers, verify that the addend source register
-        // is live here (as should have been assured above).
-        assert((!TargetRegisterInfo::isVirtualRegister(AddendSrcReg) ||
-                LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) &&
-               "Addend source register is not live!");
+	// If the addend copy is used only by this MI, then the addend source
+	// register is likely not live here. This could be fixed (based on the
+	// legality checks above, the live range for the addend source register
+	// could be extended), but it seems likely that such a trivial copy can
+	// be coalesced away later, and thus is not worth the effort.
+	if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg) &&
+            !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
+          continue;
 
         // Transform: (O2 * O3) + O1 -> (O2 * O1) + O3.
 

Added: llvm/branches/release_37/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll?rev=252476&view=auto
==============================================================================
--- llvm/branches/release_37/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll (added)
+++ llvm/branches/release_37/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll Mon Nov  9 10:24:59 2015
@@ -0,0 +1,38 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @LSH_recall_init(float %d_min, float %W) #0 {
+entry:
+  br i1 undef, label %for.body.lr.ph, label %for.end
+
+; CHECK-LABEL: @LSH_recall_init
+; CHECK: xsnmsubadp
+
+for.body.lr.ph:                                   ; preds = %entry
+  %conv3 = fpext float %W to double
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %for.body.lr.ph
+  %div = fdiv fast float 0.000000e+00, 0.000000e+00
+  %add = fadd fast float %div, %d_min
+  %conv2 = fpext float %add to double
+  %0 = tail call double @llvm.sqrt.f64(double %conv2)
+  %div4 = fdiv fast double %conv3, %0
+  %call = tail call signext i32 bitcast (i32 (...)* @p_col_helper to i32 (double)*)(double %div4) #2
+  br label %for.body
+
+for.end:                                          ; preds = %entry
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @llvm.sqrt.f64(double) #1
+
+declare signext i32 @p_col_helper(...) #2
+
+attributes #0 = { nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "target-cpu"="pwr7" "unsafe-fp-math"="true" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+