[llvm-branch-commits] [llvm-branch] r231469 - Merging r227087:
Daniel Sanders
daniel.sanders at imgtec.com
Fri Mar 6 05:09:26 PST 2015
Author: dsanders
Date: Fri Mar 6 07:09:25 2015
New Revision: 231469
URL: http://llvm.org/viewvc/llvm-project?rev=231469&view=rev
Log:
Merging r227087:
Except for the MIPS-II and MIPS-III cases since these targets were not
supported in 3.5.1.
------------------------------------------------------------------------
r227087 | vkalintiris | 2015-01-26 12:04:40 +0000 (Mon, 26 Jan 2015) | 7 lines
[mips] Add tests for bitwise binary and integer arithmetic operators.
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7125
------------------------------------------------------------------------
Added:
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/add.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/and.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/ashr.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/lshr.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/or.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sdiv.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/shl.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/srem.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sub.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/udiv.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/urem.ll
llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/xor.ll
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/add.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/add.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/add.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,83 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+
+define signext i1 @add_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: add_i1:
+
+ ; ALL: addu $[[T0:[0-9]+]], $4, $5
+ ; ALL: sll $[[T0]], $[[T0]], 31
+ ; ALL: sra $2, $[[T0]], 31
+
+ %r = add i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @add_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: add_i8:
+
+ ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5
+ ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24
+ ; NOT-R2-R6: sra $2, $[[T0]], 24
+
+ ; R2-R6: addu $[[T0:[0-9]+]], $4, $5
+ ; R2-R6: seb $2, $[[T0:[0-9]+]]
+
+ %r = add i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @add_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: add_i16:
+
+ ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5
+ ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16
+ ; NOT-R2-R6: sra $2, $[[T0]], 16
+
+ ; R2-R6: addu $[[T0:[0-9]+]], $4, $5
+ ; R2-R6: seh $2, $[[T0:[0-9]+]]
+
+ %r = add i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @add_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: add_i32:
+
+ ; ALL: addu $2, $4, $5
+
+ %r = add i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @add_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: add_i64:
+
+ ; GP32: addu $3, $5, $7
+ ; GP32: sltu $[[T0:[0-9]+]], $3, $7
+ ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6
+ ; GP32: addu $2, $4, $[[T1]]
+
+ ; GP64: daddu $2, $4, $5
+
+ %r = add i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/and.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/and.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/and.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,72 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+
+define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1:
+
+ ; ALL: and $2, $4, $5
+
+ %r = and i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @and_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8:
+
+ ; ALL: and $2, $4, $5
+
+ %r = and i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @and_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16:
+
+ ; ALL: and $2, $4, $5
+
+ %r = and i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32:
+
+ ; GP32: and $2, $4, $5
+
+ ; GP64: and $[[T0:[0-9]+]], $4, $5
+ ; GP64: sll $2, $[[T0]], 0
+
+ %r = and i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64:
+
+ ; GP32: and $2, $4, $6
+ ; GP32: and $3, $5, $7
+
+ ; GP64: and $2, $4, $5
+
+ %r = and i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/ashr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/ashr.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/ashr.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/ashr.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,105 @@
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
+; RUN: -check-prefix=32R1-R2
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=64R6 -check-prefix=R2-R6
+
+define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: ashr_i1:
+
+ ; ALL: move $2, $4
+
+ %r = ashr i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: ashr_i8:
+
+ ; FIXME: The andi instruction is redundant.
+ ; ALL: andi $[[T0:[0-9]+]], $5, 255
+ ; ALL: srav $2, $4, $[[T0]]
+
+ %r = ashr i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: ashr_i16:
+
+ ; FIXME: The andi instruction is redundant.
+ ; ALL: andi $[[T0:[0-9]+]], $5, 65535
+ ; ALL: srav $2, $4, $[[T0]]
+
+ %r = ashr i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: ashr_i32:
+
+ ; ALL: srav $2, $4, $5
+
+ %r = ashr i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: ashr_i64:
+
+ ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7
+ ; 32R1-R2: not $[[T1:[0-9]+]], $7
+ ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1
+ ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R1-R2: or $3, $[[T3]], $[[T0]]
+ ; 32R1-R2: srav $[[T4:[0-9]+]], $4, $7
+ ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R1-R2: movn $3, $[[T4]], $[[T5]]
+ ; 32R1-R2: sra $4, $4, 31
+ ; 32R1-R2: jr $ra
+ ; 32R1-R2: movn $2, $4, $[[T5]]
+
+ ; 32R6: srav $[[T0:[0-9]+]], $4, $7
+ ; 32R6: andi $[[T1:[0-9]+]], $7, 32
+ ; 32R6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]]
+ ; 32R6: sra $[[T3:[0-9]+]], $4, 31
+ ; 32R6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]]
+ ; 32R6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]]
+ ; 32R6: srlv $[[T6:[0-9]+]], $5, $7
+ ; 32R6: not $[[T7:[0-9]+]], $7
+ ; 32R6: sll $[[T8:[0-9]+]], $4, 1
+ ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+ ; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]]
+ ; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]]
+ ; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]]
+ ; 32R6: jr $ra
+ ; 32R6: or $3, $[[T0]], $[[T11]]
+
+ ; FIXME: The sll instruction below is redundant.
+ ; GP64: sll $[[T0:[0-9]+]], $5, 0
+ ; GP64: dsrav $2, $4, $[[T0]]
+
+ %r = ashr i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/lshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/lshr.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/lshr.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/lshr.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,98 @@
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
+; RUN: -check-prefix=32R1-R2
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=64R6 -check-prefix=R2-R6
+
+define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: lshr_i1:
+
+ ; ALL: move $2, $4
+
+ %r = lshr i1 %a, %b
+ ret i1 %r
+}
+
+define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {
+entry:
+; ALL-LABEL: lshr_i8:
+
+ ; ALL: srlv $[[T0:[0-9]+]], $4, $5
+ ; ALL: andi $2, $[[T0]], 255
+
+ %r = lshr i8 %a, %b
+ ret i8 %r
+}
+
+define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {
+entry:
+; ALL-LABEL: lshr_i16:
+
+ ; ALL: srlv $[[T0:[0-9]+]], $4, $5
+ ; ALL: andi $2, $[[T0]], 65535
+
+ %r = lshr i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: lshr_i32:
+
+ ; ALL: srlv $2, $4, $5
+
+ %r = lshr i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: lshr_i64:
+
+ ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7
+ ; 32R1-R2: not $[[T1:[0-9]+]], $7
+ ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1
+ ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R1-R2: or $3, $[[T3]], $[[T0]]
+ ; 32R1-R2: srlv $[[T4:[0-9]+]], $4, $7
+ ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R1-R2: movn $3, $[[T4]], $[[T5]]
+ ; 32R1-R2: jr $ra
+ ; 32R1-R2: movn $2, $zero, $[[T5]]
+
+ ; 32R6: srlv $[[T0:[0-9]+]], $5, $7
+ ; 32R6: not $[[T1:[0-9]+]], $7
+ ; 32R6: sll $[[T2:[0-9]+]], $4, 1
+ ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]]
+ ; 32R6: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]]
+ ; 32R6: srlv $[[T7:[0-9]+]], $4, $7
+ ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+ ; 32R6: or $3, $[[T8]], $[[T6]]
+ ; 32R6: jr $ra
+ ; 32R6: seleqz $2, $[[T7]], $[[T5]]
+
+ ; GP64: sll $[[T0:[0-9]+]], $5, 0
+ ; GP64: dsrlv $2, $4, $[[T0]]
+
+ %r = lshr i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/or.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/or.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/or.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,73 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+
+define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1:
+
+ ; ALL: or $2, $4, $5
+
+ %r = or i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @or_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8:
+
+ ; ALL: or $2, $4, $5
+
+ %r = or i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @or_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16:
+
+ ; ALL: or $2, $4, $5
+
+ %r = or i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32:
+
+ ; GP32: or $2, $4, $5
+
+ ; GP64: or $[[T0:[0-9]+]], $4, $5
+ ; FIXME: The sll instruction below is redundant.
+ ; GP64: sll $2, $[[T0]], 0
+
+ %r = or i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @or_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64:
+
+ ; GP32: or $2, $4, $6
+ ; GP32: or $3, $5, $7
+
+ ; GP64: or $2, $4, $5
+
+ %r = or i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sdiv.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sdiv.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sdiv.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,121 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=R6 -check-prefix=64R6
+
+define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: sdiv_i1:
+
+ ; NOT-R6: div $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mflo $[[T0:[0-9]+]]
+ ; FIXME: The sll/sra instructions are redundant since div is signed.
+ ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31
+ ; NOT-R6: sra $2, $[[T1]], 31
+
+ ; R6: div $[[T0:[0-9]+]], $4, $5
+ ; R6: teq $5, $zero, 7
+ ; FIXME: The sll/sra instructions are redundant since div is signed.
+ ; R6: sll $[[T1:[0-9]+]], $[[T0]], 31
+ ; R6: sra $2, $[[T1]], 31
+
+ %r = sdiv i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: sdiv_i8:
+
+ ; NOT-R2-R6: div $zero, $4, $5
+ ; NOT-R2-R6: teq $5, $zero, 7
+ ; NOT-R2-R6: mflo $[[T0:[0-9]+]]
+ ; FIXME: The sll/sra instructions are redundant since div is signed.
+ ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
+ ; NOT-R2-R6: sra $2, $[[T1]], 24
+
+ ; R2: div $zero, $4, $5
+ ; R2: teq $5, $zero, 7
+ ; R2: mflo $[[T0:[0-9]+]]
+ ; FIXME: This instruction is redundant.
+ ; R2: seb $2, $[[T0]]
+
+ ; R6: div $[[T0:[0-9]+]], $4, $5
+ ; R6: teq $5, $zero, 7
+ ; FIXME: This instruction is redundant.
+ ; R6: seb $2, $[[T0]]
+
+ %r = sdiv i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: sdiv_i16:
+
+ ; NOT-R2-R6: div $zero, $4, $5
+ ; NOT-R2-R6: teq $5, $zero, 7
+ ; NOT-R2-R6: mflo $[[T0:[0-9]+]]
+ ; FIXME: The sll/sra instructions are redundant since div is signed.
+ ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
+ ; NOT-R2-R6: sra $2, $[[T1]], 16
+
+ ; R2: div $zero, $4, $5
+ ; R2: teq $5, $zero, 7
+ ; R2: mflo $[[T0:[0-9]+]]
+ ; FIXME: This is instruction is redundant since div is signed.
+ ; R2: seh $2, $[[T0]]
+
+ ; R6: div $[[T0:[0-9]+]], $4, $5
+ ; R6: teq $5, $zero, 7
+ ; FIXME: This is instruction is redundant since div is signed.
+ ; R6: seh $2, $[[T0]]
+
+ %r = sdiv i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: sdiv_i32:
+
+ ; NOT-R6: div $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mflo $2
+
+ ; R6: div $2, $4, $5
+ ; R6: teq $5, $zero, 7
+
+ %r = sdiv i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: sdiv_i64:
+
+ ; GP32: lw $25, %call16(__divdi3)($gp)
+
+ ; GP64-NOT-R6: ddiv $zero, $4, $5
+ ; GP64-NOT-R6: teq $5, $zero, 7
+ ; GP64-NOT-R6: mflo $2
+
+ ; 64R6: ddiv $2, $4, $5
+ ; 64R6: teq $5, $zero, 7
+
+ %r = sdiv i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/shl.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/shl.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/shl.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,110 @@
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
+; RUN: -check-prefix=32R1-R2
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=64R6 -check-prefix=R2-R6
+
+define signext i1 @shl_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: shl_i1:
+
+ ; ALL: move $2, $4
+
+ %r = shl i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @shl_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: shl_i8:
+
+ ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
+ ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
+ ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 24
+ ; NOT-R2-R6: sra $2, $[[T2]], 24
+
+ ; R2-R6: andi $[[T0:[0-9]+]], $5, 255
+ ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
+ ; R2-R6: seb $2, $[[T1]]
+
+ %r = shl i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @shl_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: shl_i16:
+
+ ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535
+ ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
+ ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 16
+ ; NOT-R2-R6: sra $2, $[[T2]], 16
+
+ ; R2-R6: andi $[[T0:[0-9]+]], $5, 65535
+ ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
+ ; R2-R6: seh $2, $[[T1]]
+
+ %r = shl i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @shl_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: shl_i32:
+
+ ; ALL: sllv $2, $4, $5
+
+ %r = shl i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: shl_i64:
+
+ ; 32R1-R2: sllv $[[T0:[0-9]+]], $4, $7
+ ; 32R1-R2: not $[[T1:[0-9]+]], $7
+ ; 32R1-R2: srl $[[T2:[0-9]+]], $5, 1
+ ; 32R1-R2: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R1-R2: or $2, $[[T0]], $[[T3]]
+ ; 32R1-R2: sllv $[[T4:[0-9]+]], $5, $7
+ ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R1-R2: movn $2, $[[T4]], $[[T5]]
+ ; 32R1-R2: jr $ra
+ ; 32R1-R2: movn $3, $zero, $[[T5]]
+
+ ; 32R6: sllv $[[T0:[0-9]+]], $4, $7
+ ; 32R6: not $[[T1:[0-9]+]], $7
+ ; 32R6: srl $[[T2:[0-9]+]], $5, 1
+ ; 32R6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R6: or $[[T4:[0-9]+]], $[[T0]], $[[T3]]
+ ; 32R6: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T2]]
+ ; 32R6: sllv $[[T7:[0-9]+]], $5, $7
+ ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+ ; 32R6: or $2, $[[T8]], $[[T6]]
+ ; 32R6: jr $ra
+ ; 32R6: seleqz $3, $[[T7]], $[[T5]]
+
+ ; GP64: sll $[[T0:[0-9]+]], $5, 0
+ ; GP64: dsllv $2, $4, $1
+
+ %r = shl i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/srem.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/srem.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/srem.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,114 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
+; RUN: -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=R2 -check-prefix=R2-R6 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
+
+define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: srem_i1:
+
+ ; NOT-R6: div $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mfhi $[[T0:[0-9]+]]
+ ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31
+ ; NOT-R6: sra $2, $[[T1]], 31
+
+ ; R6: mod $[[T0:[0-9]+]], $4, $5
+ ; R6: teq $5, $zero, 7
+ ; R6: sll $[[T3:[0-9]+]], $[[T0]], 31
+ ; R6: sra $2, $[[T3]], 31
+
+ %r = srem i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: srem_i8:
+
+ ; NOT-R2-R6: div $zero, $4, $5
+ ; NOT-R2-R6: teq $5, $zero, 7
+ ; NOT-R2-R6: mfhi $[[T0:[0-9]+]]
+ ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
+ ; NOT-R2-R6: sra $2, $[[T1]], 24
+
+ ; R2: div $zero, $4, $5
+ ; R2: teq $5, $zero, 7
+ ; R2: mfhi $[[T0:[0-9]+]]
+ ; R2: seb $2, $[[T0]]
+
+ ; R6: mod $[[T0:[0-9]+]], $4, $5
+ ; R6: teq $5, $zero, 7
+ ; R6: seb $2, $[[T0]]
+
+ %r = srem i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: srem_i16:
+
+ ; NOT-R2-R6: div $zero, $4, $5
+ ; NOT-R2-R6: teq $5, $zero, 7
+ ; NOT-R2-R6: mfhi $[[T0:[0-9]+]]
+ ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
+ ; NOT-R2-R6: sra $2, $[[T1]], 16
+
+ ; R2: div $zero, $4, $5
+ ; R2: teq $5, $zero, 7
+ ; R2: mfhi $[[T0:[0-9]+]]
+ ; R2: seh $2, $[[T1]]
+
+ ; R6: mod $[[T0:[0-9]+]], $4, $5
+ ; R6: teq $5, $zero, 7
+ ; R6: seh $2, $[[T0]]
+
+ %r = srem i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @srem_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: srem_i32:
+
+ ; NOT-R6: div $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mfhi $2
+
+ ; R6: mod $2, $4, $5
+ ; R6: teq $5, $zero, 7
+
+ %r = srem i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: srem_i64:
+
+ ; GP32: lw $25, %call16(__moddi3)($gp)
+
+ ; GP64-NOT-R6: ddiv $zero, $4, $5
+ ; GP64-NOT-R6: teq $5, $zero, 7
+ ; GP64-NOT-R6: mfhi $2
+
+ ; 64R6: dmod $2, $4, $5
+ ; 64R6: teq $5, $zero, 7
+
+ %r = srem i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sub.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sub.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/sub.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,83 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+
+define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: sub_i1:
+
+ ; ALL: subu $[[T0:[0-9]+]], $4, $5
+ ; ALL: sll $[[T0]], $[[T0]], 31
+ ; ALL: sra $2, $[[T0]], 31
+
+ %r = sub i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: sub_i8:
+
+ ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
+ ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24
+ ; NOT-R2-R6: sra $2, $[[T0]], 24
+
+ ; R2-R6: subu $[[T0:[0-9]+]], $4, $5
+ ; R2-R6: seb $2, $[[T0:[0-9]+]]
+
+ %r = sub i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @sub_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: sub_i16:
+
+ ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
+ ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16
+ ; NOT-R2-R6: sra $2, $[[T0]], 16
+
+ ; R2-R6: subu $[[T0:[0-9]+]], $4, $5
+ ; R2-R6: seh $2, $[[T0:[0-9]+]]
+
+ %r = sub i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: sub_i32:
+
+ ; ALL: subu $2, $4, $5
+
+ %r = sub i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: sub_i64:
+
+ ; GP32: subu $3, $5, $7
+ ; GP32: sltu $[[T0:[0-9]+]], $5, $7
+ ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6
+ ; GP32: subu $2, $4, $[[T1]]
+
+ ; GP64: dsubu $2, $4, $5
+
+ %r = sub i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/udiv.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/udiv.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/udiv.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,93 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=R6 -check-prefix=64R6
+
+define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
+entry:
+; ALL-LABEL: udiv_i1:
+
+ ; NOT-R6: divu $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mflo $2
+
+ ; R6: divu $2, $4, $5
+ ; R6: teq $5, $zero, 7
+
+ %r = udiv i1 %a, %b
+ ret i1 %r
+}
+
+define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
+entry:
+; ALL-LABEL: udiv_i8:
+
+ ; NOT-R6: divu $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mflo $2
+
+ ; R6: divu $2, $4, $5
+ ; R6: teq $5, $zero, 7
+
+ %r = udiv i8 %a, %b
+ ret i8 %r
+}
+
+define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
+entry:
+; ALL-LABEL: udiv_i16:
+
+ ; NOT-R6: divu $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mflo $2
+
+ ; R6: divu $2, $4, $5
+ ; R6: teq $5, $zero, 7
+
+ %r = udiv i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: udiv_i32:
+
+ ; NOT-R6: divu $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mflo $2
+
+ ; R6: divu $2, $4, $5
+ ; R6: teq $5, $zero, 7
+
+ %r = udiv i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: udiv_i64:
+
+ ; GP32: lw $25, %call16(__udivdi3)($gp)
+
+ ; GP64-NOT-R6: ddivu $zero, $4, $5
+ ; GP64-NOT-R6: teq $5, $zero, 7
+ ; GP64-NOT-R6: mflo $2
+
+ ; 64R6: ddivu $2, $4, $5
+ ; 64R6: teq $5, $zero, 7
+
+ %r = udiv i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/urem.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/urem.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/urem.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,130 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
+; RUN: -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=R2 -check-prefix=R2-R6 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
+
+define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: urem_i1:
+
+ ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1
+ ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1
+ ; NOT-R6: divu $zero, $[[T1]], $[[T0]]
+ ; NOT-R6: teq $[[T0]], $zero, 7
+ ; NOT-R6: mfhi $[[T2:[0-9]+]]
+ ; NOT-R6: sll $[[T3:[0-9]+]], $[[T2]], 31
+ ; NOT-R6: sra $2, $[[T3]], 31
+
+ ; R6: andi $[[T0:[0-9]+]], $5, 1
+ ; R6: andi $[[T1:[0-9]+]], $4, 1
+ ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+ ; R6: teq $[[T0]], $zero, 7
+ ; R6: sll $[[T3:[0-9]+]], $[[T2]], 31
+ ; R6: sra $2, $[[T3]], 31
+
+ %r = urem i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: urem_i8:
+
+ ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
+ ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255
+ ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
+ ; NOT-R2-R6: teq $[[T0]], $zero, 7
+ ; NOT-R2-R6: mfhi $[[T2:[0-9]+]]
+ ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 24
+ ; NOT-R2-R6: sra $2, $[[T3]], 24
+
+ ; R2: andi $[[T0:[0-9]+]], $5, 255
+ ; R2: andi $[[T1:[0-9]+]], $4, 255
+ ; R2: divu $zero, $[[T1]], $[[T0]]
+ ; R2: teq $[[T0]], $zero, 7
+ ; R2: mfhi $[[T2:[0-9]+]]
+ ; R2: seb $2, $[[T2]]
+
+ ; R6: andi $[[T0:[0-9]+]], $5, 255
+ ; R6: andi $[[T1:[0-9]+]], $4, 255
+ ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+ ; R6: teq $[[T0]], $zero, 7
+ ; R6: seb $2, $[[T2]]
+
+ %r = urem i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: urem_i16:
+
+ ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535
+ ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 65535
+ ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
+ ; NOT-R2-R6: teq $[[T0]], $zero, 7
+ ; NOT-R2-R6: mfhi $[[T2:[0-9]+]]
+ ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 16
+ ; NOT-R2-R6: sra $2, $[[T3]], 16
+
+ ; R2: andi $[[T0:[0-9]+]], $5, 65535
+ ; R2: andi $[[T1:[0-9]+]], $4, 65535
+ ; R2: divu $zero, $[[T1]], $[[T0]]
+ ; R2: teq $[[T0]], $zero, 7
+ ; R2: mfhi $[[T3:[0-9]+]]
+ ; R2: seh $2, $[[T2]]
+
+ ; R6: andi $[[T0:[0-9]+]], $5, 65535
+ ; R6: andi $[[T1:[0-9]+]], $4, 65535
+ ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+ ; R6: teq $[[T0]], $zero, 7
+ ; R6: seh $2, $[[T2]]
+
+ %r = urem i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @urem_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: urem_i32:
+
+ ; NOT-R6: divu $zero, $4, $5
+ ; NOT-R6: teq $5, $zero, 7
+ ; NOT-R6: mfhi $2
+
+ ; R6: modu $2, $4, $5
+ ; R6: teq $5, $zero, 7
+
+ %r = urem i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @urem_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: urem_i64:
+
+ ; GP32: lw $25, %call16(__umoddi3)($gp)
+
+ ; GP64-NOT-R6: ddivu $zero, $4, $5
+ ; GP64-NOT-R6: teq $5, $zero, 7
+ ; GP64-NOT-R6: mfhi $2
+
+ ; 64R6: dmodu $2, $4, $5
+ ; 64R6: teq $5, $zero, 7
+
+ %r = urem i64 %a, %b
+ ret i64 %r
+}
Added: llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/xor.ll?rev=231469&view=auto
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/xor.ll (added)
+++ llvm/branches/release_35/test/CodeGen/Mips/llvm-ir/xor.ll Fri Mar 6 07:09:25 2015
@@ -0,0 +1,72 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+
+define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: xor_i1:
+
+ ; ALL: xor $2, $4, $5
+
+ %r = xor i1 %a, %b
+ ret i1 %r
+}
+
+define signext i8 @xor_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: xor_i8:
+
+ ; ALL: xor $2, $4, $5
+
+ %r = xor i8 %a, %b
+ ret i8 %r
+}
+
+define signext i16 @xor_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: xor_i16:
+
+ ; ALL: xor $2, $4, $5
+
+ %r = xor i16 %a, %b
+ ret i16 %r
+}
+
+define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: xor_i32:
+
+ ; GP32: xor $2, $4, $5
+
+ ; GP64: xor $[[T0:[0-9]+]], $4, $5
+ ; GP64: sll $2, $[[T0]], 0
+
+ %r = xor i32 %a, %b
+ ret i32 %r
+}
+
+define signext i64 @xor_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: xor_i64:
+
+ ; GP32: xor $2, $4, $6
+ ; GP32: xor $3, $5, $7
+
+ ; GP64: xor $2, $4, $5
+
+ %r = xor i64 %a, %b
+ ret i64 %r
+}
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