[llvm-branch-commits] [llvm-branch] r243646 - Merging r243469:
Hans Wennborg
hans at hanshq.net
Thu Jul 30 09:14:05 PDT 2015
Author: hans
Date: Thu Jul 30 11:14:05 2015
New Revision: 243646
URL: http://llvm.org/viewvc/llvm-project?rev=243646&view=rev
Log:
Merging r243469:
------------------------------------------------------------------------
r243469 | vkalintiris | 2015-07-28 12:57:25 -0700 (Tue, 28 Jul 2015) | 12 lines
[mips][FastISel] Fix generated code for IR's select instruction.
Summary:
Generate correct code for the select instruction by zero-extending
it's boolean/condition operand to GPR-width. This is necessary because
the conditional-move instructions operate on the whole register.
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11506
------------------------------------------------------------------------
Modified:
llvm/branches/release_37/ (props changed)
llvm/branches/release_37/lib/Target/Mips/MipsFastISel.cpp
llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll
Propchange: llvm/branches/release_37/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Jul 30 11:14:05 2015
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243116,243263,243294,243361,243500,243519,243531
+/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243116,243263,243294,243361,243469,243500,243519,243531
Modified: llvm/branches/release_37/lib/Target/Mips/MipsFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/Mips/MipsFastISel.cpp?rev=243646&r1=243645&r2=243646&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/branches/release_37/lib/Target/Mips/MipsFastISel.cpp Thu Jul 30 11:14:05 2015
@@ -981,6 +981,13 @@ bool MipsFastISel::selectSelect(const In
if (!Src1Reg || !Src2Reg || !CondReg)
return false;
+ unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
+ if (!ZExtCondReg)
+ return false;
+
+ if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
+ return false;
+
unsigned ResultReg = createResultReg(RC);
unsigned TempReg = createResultReg(RC);
@@ -989,7 +996,7 @@ bool MipsFastISel::selectSelect(const In
emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
emitInst(CondMovOpc, ResultReg)
- .addReg(Src1Reg).addReg(CondReg).addReg(TempReg);
+ .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
updateValueMap(I, ResultReg);
return true;
}
Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll?rev=243646&r1=243645&r2=243646&view=diff
==============================================================================
--- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll (original)
+++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll Thu Jul 30 11:14:05 2015
@@ -8,7 +8,8 @@ entry:
; FIXME: The following instruction is redundant.
; CHECK: xor $[[T0:[0-9]+]], $4, $zero
; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK-NEXT: movn $6, $5, $[[T1]]
+ ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
+ ; CHECK-NEXT: movn $6, $5, $[[T2]]
; CHECK: move $2, $6
%cond = icmp ne i1 %j, 0
%res = select i1 %cond, i1 %k, i1 %l
@@ -24,7 +25,8 @@ entry:
; CHECK-DAG: seb $[[T1:[0-9]+]], $zero
; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]]
; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
- ; CHECK-NEXT: movn $6, $5, $[[T3]]
+ ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
+ ; CHECK-NEXT: movn $6, $5, $[[T4]]
; CHECK: move $2, $6
%cond = icmp ne i8 %j, 0
%res = select i1 %cond, i8 %k, i8 %l
@@ -40,7 +42,8 @@ entry:
; CHECK-DAG: seh $[[T1:[0-9]+]], $zero
; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]]
; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
- ; CHECK-NEXT: movn $6, $5, $[[T3]]
+ ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
+ ; CHECK-NEXT: movn $6, $5, $[[T4]]
; CHECK: move $2, $6
%cond = icmp ne i16 %j, 0
%res = select i1 %cond, i16 %k, i16 %l
@@ -54,7 +57,8 @@ entry:
; FIXME: The following instruction is redundant.
; CHECK: xor $[[T0:[0-9]+]], $4, $zero
; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK-NEXT: movn $6, $5, $[[T1]]
+ ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
+ ; CHECK-NEXT: movn $6, $5, $[[T2]]
; CHECK: move $2, $6
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, i32 %k, i32 %l
@@ -69,7 +73,8 @@ entry:
; CHECK-DAG: mtc1 $5, $f1
; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero
; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK: movn.s $f0, $f1, $[[T1]]
+ ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
+ ; CHECK: movn.s $f0, $f1, $[[T2]]
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, float %k, float %l
ret float %res
@@ -84,7 +89,8 @@ entry:
; CHECK-DAG: ldc1 $f0, 16($sp)
; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero
; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK: movn.d $f0, $f2, $[[T1]]
+ ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
+ ; CHECK: movn.d $f0, $f2, $[[T2]]
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, double %k, double %l
ret double %res
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