[llvm-branch-commits] [llvm-branch] r243528 - Merging r243519:

[Hans Wennborg]

Author: hans
Date: Wed Jul 29 10:58:34 2015
New Revision: 243528

URL: http://llvm.org/viewvc/llvm-project?rev=243528&view=rev
Log:
Merging r243519:
------------------------------------------------------------------------
r243519 | wschmidt | 2015-07-29 07:31:57 -0700 (Wed, 29 Jul 2015) | 14 lines

[PPC] Fix PR24216: Don't generate splat for misaligned shuffle mask

Given certain shuffle-vector masks, LLVM emits splat instructions
which splat the wrong bytes from the source register.  The issue is
that the function PPC::isSplatShuffleMask() in PPCISelLowering.cpp
does not ensure that the splat pattern found is requesting bytes that
are aligned on an EltSize boundary.  This patch detects this situation
as not a valid splat mask, resulting in a permute being generated
instead of a splat.

Patch and test case by Tyler Kenney, cleaned up a bit by me.

This is a simple bug fix that would be good to incorporate into 3.7.

------------------------------------------------------------------------

Added:
    llvm/branches/release_37/test/CodeGen/PowerPC/pr24216.ll
      - copied unchanged from r243519, llvm/trunk/test/CodeGen/PowerPC/pr24216.ll
Modified:
    llvm/branches/release_37/   (props changed)
    llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp

Propchange: llvm/branches/release_37/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jul 29 10:58:34 2015
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243116,243263,243294,243361,243500
+/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243116,243263,243294,243361,243500,243519

Modified: llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp?rev=243528&r1=243527&r2=243528&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp Wed Jul 29 10:58:34 2015
@@ -1430,6 +1430,11 @@ bool PPC::isSplatShuffleMask(ShuffleVect
   assert(N->getValueType(0) == MVT::v16i8 &&
          (EltSize == 1 || EltSize == 2 || EltSize == 4));
 
+  // The consecutive indices need to specify an element, not part of two
+  // different elements.  So abandon ship early if this isn't the case.
+  if (N->getMaskElt(0) % EltSize != 0)
+    return false;
+
   // This is a splat operation if each element of the permute is the same, and
   // if the value doesn't reference the second vector.
   unsigned ElementBase = N->getMaskElt(0);