[llvm-branch-commits] [llvm-branch] r242327 - Merging r242288:
Hans Wennborg
hans at hanshq.net
Wed Jul 15 13:35:58 PDT 2015
Author: hans
Date: Wed Jul 15 15:35:58 2015
New Revision: 242327
URL: http://llvm.org/viewvc/llvm-project?rev=242327&view=rev
Log:
Merging r242288:
------------------------------------------------------------------------
r242288 | d0k | 2015-07-15 05:56:19 -0700 (Wed, 15 Jul 2015) | 3 lines
[PPC] Disassemble little endian ppc instructions in the right byte order
PR24122. The test is simply a byte swapped version of ppc64-encoding.txt.
------------------------------------------------------------------------
Added:
llvm/branches/release_37/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
- copied unchanged from r242288, llvm/trunk/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
Modified:
llvm/branches/release_37/ (props changed)
llvm/branches/release_37/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
Propchange: llvm/branches/release_37/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jul 15 15:35:58 2015
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,242239
+/llvm/trunk:155241,242239,242288
Modified: llvm/branches/release_37/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp?rev=242327&r1=242326&r2=242327&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (original)
+++ llvm/branches/release_37/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp Wed Jul 15 15:35:58 2015
@@ -12,6 +12,7 @@
#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Endian.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
@@ -22,10 +23,12 @@ typedef MCDisassembler::DecodeStatus Dec
namespace {
class PPCDisassembler : public MCDisassembler {
+ bool IsLittleEndian;
+
public:
- PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
- : MCDisassembler(STI, Ctx) {}
- ~PPCDisassembler() override {}
+ PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
+ bool IsLittleEndian)
+ : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
@@ -37,7 +40,13 @@ public:
static MCDisassembler *createPPCDisassembler(const Target &T,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
- return new PPCDisassembler(STI, Ctx);
+ return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
+}
+
+static MCDisassembler *createPPCLEDisassembler(const Target &T,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx) {
+ return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
}
extern "C" void LLVMInitializePowerPCDisassembler() {
@@ -47,7 +56,7 @@ extern "C" void LLVMInitializePowerPCDis
TargetRegistry::RegisterMCDisassembler(ThePPC64Target,
createPPCDisassembler);
TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget,
- createPPCDisassembler);
+ createPPCLEDisassembler);
}
// FIXME: These can be generated by TableGen from the existing register
@@ -383,9 +392,9 @@ DecodeStatus PPCDisassembler::getInstruc
return MCDisassembler::Fail;
}
- // The instruction is big-endian encoded.
- uint32_t Inst =
- (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);
+ // Read the instruction in the proper endianness.
+ uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data())
+ : support::endian::read32be(Bytes.data());
if (STI.getFeatureBits()[PPC::FeatureQPX]) {
DecodeStatus result =
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