[llvm-branch-commits] [llvm-branch] r227597 - Merging r227462:

[Tom Stellard]

Author: tstellar
Date: Fri Jan 30 12:55:32 2015
New Revision: 227597

URL: http://llvm.org/viewvc/llvm-project?rev=227597&view=rev
Log:
Merging r227462:

------------------------------------------------------------------------
r227462 | thomas.stellard | 2015-01-29 11:55:28 -0500 (Thu, 29 Jan 2015) | 2 lines

R600/SI: Remove stray debug statements

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp

Modified: llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp?rev=227597&r1=227596&r2=227597&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp Fri Jan 30 12:55:32 2015
@@ -23,7 +23,6 @@
 #include "llvm/IR/Function.h"
 #include "llvm/IR/LLVMContext.h"
 
-#include "llvm/Support/Debug.h"
 using namespace llvm;
 
 SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
@@ -140,7 +139,6 @@ void SIRegisterInfo::buildScratchLoadSto
   unsigned Size = NumSubRegs * 4;
 
   if (!isUInt<12>(Offset + Size)) {
-    dbgs() << "Offset scavenge\n";
     SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
     if (SOffset == AMDGPU::NoRegister) {
       RanOutOfSGPRs = true;
@@ -235,10 +233,8 @@ void SIRegisterInfo::eliminateFrameIndex
            Ctx.emitError("Ran out of VGPRs for spilling SGPR");
         }
 
-        if (isM0) {
-          dbgs() << "Scavenge M0\n";
+        if (isM0)
           SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
-        }
 
         BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
                 .addReg(Spill.VGPR)