[llvm-branch-commits] [llvm-branch] r227364 - Merging r226945:

[Tom Stellard]

Author: tstellar
Date: Wed Jan 28 14:46:14 2015
New Revision: 227364

URL: http://llvm.org/viewvc/llvm-project?rev=227364&view=rev
Log:
Merging r226945:

------------------------------------------------------------------------
r226945 | thomas.stellard | 2015-01-23 17:05:45 -0500 (Fri, 23 Jan 2015) | 9 lines

R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()

We used to do this promotion during DAG legalization, but this
caused an infinite loop in ExpandUnalignedLoad() because it assumed
that i64 loads were legal if i64 was a legal type.

It also seems better to report i64 loads as legal, since they actually
are and we were just promoting them to simplify our tablegen files.

------------------------------------------------------------------------

Added:
    llvm/branches/release_36/test/CodeGen/R600/misaligned-load.ll
Modified:
    llvm/branches/release_36/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
    llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp

Modified: llvm/branches/release_36/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/AMDGPUISelDAGToDAG.cpp?rev=227364&r1=227363&r2=227364&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/AMDGPUISelDAGToDAG.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/AMDGPUISelDAGToDAG.cpp Wed Jan 28 14:46:14 2015
@@ -417,6 +417,28 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNod
                                   N->getValueType(0), Ops);
   }
 
+  case ISD::LOAD: {
+    // To simplify the TableGen patters, we replace all i64 loads with
+    // v2i32 loads.  Alternatively, we could promote i64 loads to v2i32
+    // during DAG legalization, however, so places (ExpandUnalignedLoad)
+    // in the DAG legalizer assume that if i64 is legal, so doing this
+    // promotion early can cause problems.
+    EVT VT = N->getValueType(0);
+    LoadSDNode *LD = cast<LoadSDNode>(N);
+    if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD)
+      break;
+
+    SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SDLoc(N), LD->getChain(),
+                                     LD->getBasePtr(), LD->getMemOperand());
+    SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SDLoc(N),
+                                      MVT::i64, NewLoad);
+    CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLoad.getValue(1));
+    CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), BitCast);
+    SelectCode(NewLoad.getNode());
+    N = BitCast.getNode();
+    break;
+  }
+
   case AMDGPUISD::REGISTER_LOAD: {
     if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
       break;

Modified: llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp?rev=227364&r1=227363&r2=227364&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp Wed Jan 28 14:46:14 2015
@@ -187,9 +187,6 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri
   setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
   AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
 
-  setOperationAction(ISD::LOAD, MVT::i64, Promote);
-  AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
-
   setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
   AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
 

Added: llvm/branches/release_36/test/CodeGen/R600/misaligned-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/R600/misaligned-load.ll?rev=227364&view=auto
==============================================================================
--- llvm/branches/release_36/test/CodeGen/R600/misaligned-load.ll (added)
+++ llvm/branches/release_36/test/CodeGen/R600/misaligned-load.ll Wed Jan 28 14:46:14 2015
@@ -0,0 +1,18 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+
+; SI: @byte_aligned_load64
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: s_endpgm
+define void @byte_aligned_load64(i64 addrspace(1)* %out, i64 addrspace(3)* %in) {
+entry:
+  %0 = load i64 addrspace(3)* %in, align 1
+  store i64 %0, i64 addrspace(1)* %out
+  ret void
+}