[llvm-branch-commits] [llvm-branch] r226727 - Merging r226596:

[Tom Stellard]

Author: tstellar
Date: Wed Jan 21 16:44:51 2015
New Revision: 226727

URL: http://llvm.org/viewvc/llvm-project?rev=226727&view=rev
Log:
Merging r226596:

------------------------------------------------------------------------
r226596 | thomas.stellard | 2015-01-20 14:33:02 -0500 (Tue, 20 Jan 2015) | 2 lines

R600/SI: Fix simple-loop.ll test

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/SIPrepareScratchRegs.cpp
    llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp
    llvm/branches/release_36/test/CodeGen/R600/basic-loop.ll

Modified: llvm/branches/release_36/lib/Target/R600/SIPrepareScratchRegs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIPrepareScratchRegs.cpp?rev=226727&r1=226726&r2=226727&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIPrepareScratchRegs.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIPrepareScratchRegs.cpp Wed Jan 21 16:44:51 2015
@@ -99,7 +99,9 @@ bool SIPrepareScratchRegs::runOnMachineF
     ScratchOffsetFI = FrameInfo->CreateSpillStackObject(4,4);
     BuildMI(*Entry, I, DL, TII->get(AMDGPU::SI_SPILL_S32_SAVE))
             .addReg(ScratchOffsetPreloadReg)
-            .addFrameIndex(ScratchOffsetFI);
+            .addFrameIndex(ScratchOffsetFI)
+            .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
+            .addReg(AMDGPU::SGPR0, RegState::Undef);
   }
 
 
@@ -116,7 +118,8 @@ bool SIPrepareScratchRegs::runOnMachineF
     MachineBasicBlock &MBB = *BI;
     // Add the scratch offset reg as a live-in so that the register scavenger
     // doesn't re-use it.
-    if (!MBB.isLiveIn(ScratchOffsetReg))
+    if (!MBB.isLiveIn(ScratchOffsetReg) &&
+        ScratchOffsetReg != AMDGPU::NoRegister)
       MBB.addLiveIn(ScratchOffsetReg);
     RS.enterBasicBlock(&MBB);
 
@@ -173,8 +176,8 @@ bool SIPrepareScratchRegs::runOnMachineF
             BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
                     ScratchOffsetReg)
                     .addFrameIndex(ScratchOffsetFI)
-                    .addReg(AMDGPU::NoRegister)
-                    .addReg(AMDGPU::NoRegister);
+                    .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
+                    .addReg(AMDGPU::SGPR0, RegState::Undef);
           } else if (!MBB.isLiveIn(ScratchOffsetReg)) {
             MBB.addLiveIn(ScratchOffsetReg);
           }
@@ -191,6 +194,7 @@ bool SIPrepareScratchRegs::runOnMachineF
           MI.getOperand(2).setIsUndef(false);
           MI.getOperand(3).setReg(ScratchOffsetReg);
           MI.getOperand(3).setIsUndef(false);
+          MI.getOperand(3).setIsKill(false);
           MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
           MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
           MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));

Modified: llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp?rev=226727&r1=226726&r2=226727&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp Wed Jan 21 16:44:51 2015
@@ -142,7 +142,7 @@ void SIRegisterInfo::buildScratchLoadSto
             .addReg(SubReg, getDefRegState(IsLoad))
             .addReg(ScratchRsrcReg, getKillRegState(IsKill))
             .addImm(Offset)
-            .addReg(SOffset, getKillRegState(IsKill))
+            .addReg(SOffset)
             .addImm(0) // glc
             .addImm(0) // slc
             .addImm(0) // tfe

Modified: llvm/branches/release_36/test/CodeGen/R600/basic-loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/R600/basic-loop.ll?rev=226727&r1=226726&r2=226727&view=diff
==============================================================================
--- llvm/branches/release_36/test/CodeGen/R600/basic-loop.ll (original)
+++ llvm/branches/release_36/test/CodeGen/R600/basic-loop.ll Wed Jan 21 16:44:51 2015
@@ -1,4 +1,3 @@
-; XFAIL: *
 ; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s
 
 ; CHECK-LABEL: {{^}}test_loop: