[llvm-branch-commits] [llvm-branch] r236071 - Merging r233080:
Tom Stellard
thomas.stellard at amd.com
Tue Apr 28 17:59:49 PDT 2015
Author: tstellar
Date: Tue Apr 28 19:59:49 2015
New Revision: 236071
URL: http://llvm.org/viewvc/llvm-project?rev=236071&view=rev
Log:
Merging r233080:
------------------------------------------------------------------------
r233080 | marek.olsak | 2015-03-24 09:40:38 -0400 (Tue, 24 Mar 2015) | 4 lines
R600/SI: Insert more NOPs after READLANE on VI, don't use NOPs on CI
This is a candidate for stable.
------------------------------------------------------------------------
Modified:
llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp
Modified: llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp?rev=236071&r1=236070&r2=236071&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp Tue Apr 28 19:59:49 2015
@@ -266,7 +266,22 @@ void SIRegisterInfo::eliminateFrameIndex
.addReg(SubReg);
}
}
- TII->insertNOPs(MI, 3);
+
+ // TODO: only do this when it is needed
+ switch (ST.getGeneration()) {
+ case AMDGPUSubtarget::SOUTHERN_ISLANDS:
+ // "VALU writes SGPR" -> "SMRD reads that SGPR" needs "S_NOP 3" on SI
+ TII->insertNOPs(MI, 3);
+ break;
+ case AMDGPUSubtarget::SEA_ISLANDS:
+ break;
+ default: // VOLCANIC_ISLANDS and later
+ // "VALU writes SGPR -> VMEM reads that SGPR" needs "S_NOP 4" on VI
+ // and later. This also applies to VALUs which write VCC, but we're
+ // unlikely to see VMEM use VCC.
+ TII->insertNOPs(MI, 4);
+ }
+
MI->eraseFromParent();
break;
}
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