[llvm-branch-commits] [llvm-branch] r236040 - Merging r232386:

[Tom Stellard]

Author: tstellar
Date: Tue Apr 28 16:23:04 2015
New Revision: 236040

URL: http://llvm.org/viewvc/llvm-project?rev=236040&view=rev
Log:
Merging r232386:

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r232386 | thomas.stellard | 2015-03-16 11:53:55 -0400 (Mon, 16 Mar 2015) | 8 lines

R600/SI: don't try min3/max3/med3 with f64

There are no opcodes for this. This also adds a test case.

v2: make test more robust

Patch by: Grigori Goronzy

------------------------------------------------------------------------

Added:
    llvm/branches/release_36/test/CodeGen/R600/fmax3.f64.ll
Modified:
    llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp

Modified: llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp?rev=236040&r1=236039&r2=236040&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp Tue Apr 28 16:23:04 2015
@@ -1584,6 +1584,7 @@ SDValue SITargetLowering::PerformDAGComb
   case AMDGPUISD::UMAX:
   case AMDGPUISD::UMIN: {
     if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
+        N->getValueType(0) != MVT::f64 &&
         getTargetMachine().getOptLevel() > CodeGenOpt::None)
       return performMin3Max3Combine(N, DCI);
     break;

Added: llvm/branches/release_36/test/CodeGen/R600/fmax3.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/R600/fmax3.f64.ll?rev=236040&view=auto
==============================================================================
--- llvm/branches/release_36/test/CodeGen/R600/fmax3.f64.ll (added)
+++ llvm/branches/release_36/test/CodeGen/R600/fmax3.f64.ll Tue Apr 28 16:23:04 2015
@@ -0,0 +1,24 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+
+declare double @llvm.maxnum.f64(double, double) nounwind readnone
+
+; SI-LABEL: {{^}}test_fmax3_f64:
+; SI-DAG: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0{{$}}
+; SI-DAG: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0 offset:8
+; SI-DAG: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0 offset:16
+; SI: v_max_f64 [[REGA]], [[REGA]], [[REGB]]
+; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGC]]
+; SI: buffer_store_dwordx2 [[RESULT]],
+; SI: s_endpgm
+define void @test_fmax3_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
+  %bptr = getelementptr double addrspace(1)* %aptr, i32 1
+  %cptr = getelementptr double addrspace(1)* %aptr, i32 2
+  %a = load double addrspace(1)* %aptr, align 8
+  %b = load double addrspace(1)* %bptr, align 8
+  %c = load double addrspace(1)* %cptr, align 8
+  %f0 = call double @llvm.maxnum.f64(double %a, double %b) nounwind readnone
+  %f1 = call double @llvm.maxnum.f64(double %f0, double %c) nounwind readnone
+  store double %f1, double addrspace(1)* %out, align 8
+  ret void
+}