[llvm-branch-commits] [llvm-branch] r236038 - Merging r231659:
Tom Stellard
thomas.stellard at amd.com
Tue Apr 28 14:23:00 PDT 2015
Author: tstellar
Date: Tue Apr 28 16:23:00 2015
New Revision: 236038
URL: http://llvm.org/viewvc/llvm-project?rev=236038&view=rev
Log:
Merging r231659:
------------------------------------------------------------------------
r231659 | marek.olsak | 2015-03-09 11:48:09 -0400 (Mon, 09 Mar 2015) | 4 lines
R600/SI: Limit SGPRs to 80 on Tonga and Iceland
This is a candidate for stable.
------------------------------------------------------------------------
Modified:
llvm/branches/release_36/lib/Target/R600/AMDGPU.td
llvm/branches/release_36/lib/Target/R600/AMDGPUAsmPrinter.cpp
llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.cpp
llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.h
llvm/branches/release_36/lib/Target/R600/Processors.td
llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp
llvm/branches/release_36/test/CodeGen/R600/elf.ll
Modified: llvm/branches/release_36/lib/Target/R600/AMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/AMDGPU.td?rev=236038&r1=236037&r2=236038&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/AMDGPU.td (original)
+++ llvm/branches/release_36/lib/Target/R600/AMDGPU.td Tue Apr 28 16:23:00 2015
@@ -97,6 +97,11 @@ def FeatureVGPRSpilling : SubtargetFeatu
"true",
"Enable spilling of VGPRs to scratch memory">;
+def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
+ "SGPRInitBug",
+ "true",
+ "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
+
class SubtargetFeatureFetchLimit <string Value> :
SubtargetFeature <"fetch"#Value,
"TexVTXClauseSize",
Modified: llvm/branches/release_36/lib/Target/R600/AMDGPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/AMDGPUAsmPrinter.cpp?rev=236038&r1=236037&r2=236038&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/AMDGPUAsmPrinter.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/AMDGPUAsmPrinter.cpp Tue Apr 28 16:23:00 2015
@@ -343,6 +343,13 @@ void AMDGPUAsmPrinter::getSIProgramInfo(
ProgInfo.NumVGPR = MaxVGPR + 1;
ProgInfo.NumSGPR = MaxSGPR + 1;
+ if (STM.hasSGPRInitBug()) {
+ if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG)
+ llvm_unreachable("Too many SGPRs used with the SGPR init bug");
+
+ ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
+ }
+
ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
// Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
Modified: llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.cpp?rev=236038&r1=236037&r2=236038&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.cpp Tue Apr 28 16:23:00 2015
@@ -80,7 +80,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringR
FlatAddressSpace(false), EnableIRStructurizer(true),
EnablePromoteAlloca(false), EnableIfCvt(true),
EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
- EnableVGPRSpilling(false),
+ EnableVGPRSpilling(false),SGPRInitBug(false),
DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))),
FrameLowering(TargetFrameLowering::StackGrowsUp,
64 * 16, // Maximum stack alignment (long16)
Modified: llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.h?rev=236038&r1=236037&r2=236038&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.h (original)
+++ llvm/branches/release_36/lib/Target/R600/AMDGPUSubtarget.h Tue Apr 28 16:23:00 2015
@@ -45,6 +45,10 @@ public:
VOLCANIC_ISLANDS,
};
+ enum {
+ FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
+ };
+
private:
std::string DevName;
bool Is64bit;
@@ -66,6 +70,7 @@ private:
bool CFALUBug;
int LocalMemorySize;
bool EnableVGPRSpilling;
+ bool SGPRInitBug;
const DataLayout DL;
AMDGPUFrameLowering FrameLowering;
@@ -203,6 +208,10 @@ public:
return LocalMemorySize;
}
+ bool hasSGPRInitBug() const {
+ return SGPRInitBug;
+ }
+
unsigned getAmdKernelCodeChipID() const;
bool enableMachineScheduler() const override {
Modified: llvm/branches/release_36/lib/Target/R600/Processors.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/Processors.td?rev=236038&r1=236037&r2=236038&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/Processors.td (original)
+++ llvm/branches/release_36/lib/Target/R600/Processors.td Tue Apr 28 16:23:00 2015
@@ -113,8 +113,12 @@ def : ProcessorModel<"mullins", SIQua
// Volcanic Islands
//===----------------------------------------------------------------------===//
-def : ProcessorModel<"tonga", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
+def : ProcessorModel<"tonga", SIQuarterSpeedModel,
+ [FeatureVolcanicIslands, FeatureSGPRInitBug]
+>;
-def : ProcessorModel<"iceland", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
+def : ProcessorModel<"iceland", SIQuarterSpeedModel,
+ [FeatureVolcanicIslands, FeatureSGPRInitBug]
+>;
def : ProcessorModel<"carrizo", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
Modified: llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp?rev=236038&r1=236037&r2=236038&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp Tue Apr 28 16:23:00 2015
@@ -46,6 +46,23 @@ BitVector SIRegisterInfo::getReservedReg
Reserved.set(AMDGPU::VGPR255);
Reserved.set(AMDGPU::VGPR254);
+ // Tonga and Iceland can only allocate a fixed number of SGPRs due
+ // to a hw bug.
+ if (ST.hasSGPRInitBug()) {
+ unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
+ // Reserve some SGPRs for FLAT_SCRATCH and VCC (4 SGPRs).
+ // Assume XNACK_MASK is unused.
+ unsigned Limit = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG - 4;
+
+ for (unsigned i = Limit; i < NumSGPRs; ++i) {
+ unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
+ MCRegAliasIterator R = MCRegAliasIterator(Reg, this, true);
+
+ for (; R.isValid(); ++R)
+ Reserved.set(*R);
+ }
+ }
+
return Reserved;
}
Modified: llvm/branches/release_36/test/CodeGen/R600/elf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/R600/elf.ll?rev=236038&r1=236037&r2=236038&view=diff
==============================================================================
--- llvm/branches/release_36/test/CodeGen/R600/elf.ll (original)
+++ llvm/branches/release_36/test/CodeGen/R600/elf.ll Tue Apr 28 16:23:00 2015
@@ -1,7 +1,9 @@
; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG %s
+; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG %s
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TONGA %s
+; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
+; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
; ELF: Format: ELF32
; ELF: Name: .AMDGPU.config
@@ -15,7 +17,8 @@
; CONFIG: test:
; CONFIG: .section .AMDGPU.config
; CONFIG-NEXT: .long 45096
-; CONFIG-NEXT: .long 0
+; TYPICAL-NEXT: .long 0
+; TONGA-NEXT: .long 576
define void @test(i32 %p) #0 {
%i = add i32 %p, 2
%r = bitcast i32 %i to float
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