[llvm-branch-commits] [llvm-branch] r235684 - Merging r229235:

[Tom Stellard]

Author: tstellar
Date: Thu Apr 23 20:30:51 2015
New Revision: 235684

URL: http://llvm.org/viewvc/llvm-project?rev=235684&view=rev
Log:
Merging r229235:

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r229235 | Matthew.Arsenault | 2015-02-13 23:03:18 -0500 (Fri, 13 Feb 2015) | 2 lines

R600/SI: Fix schedule model for v_div_scale_{f32|f64}

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Modified:
    llvm/branches/release_36/lib/Target/R600/SIInstructions.td

Modified: llvm/branches/release_36/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstructions.td?rev=235684&r1=235683&r2=235684&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstructions.td (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstructions.td Thu Apr 23 20:30:51 2015
@@ -1733,9 +1733,11 @@ defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c
 
 } // isCommutable = 1, SchedRW = [WriteQuarterRate32]
 
+let SchedRW = [WriteFloatFMA, WriteSALU] in {
 defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d, 0x1e0>, "v_div_scale_f32", []>;
+}
 
-let SchedRW = [WriteDouble] in {
+let SchedRW = [WriteDouble, WriteSALU] in {
 // Double precision division pre-scale.
 defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e, 0x1e1>, "v_div_scale_f64", []>;
 } // let SchedRW = [WriteDouble]