[llvm-branch-commits] [llvm-branch] r235624 - Merging r229227:

[Tom Stellard]

Author: tstellar
Date: Thu Apr 23 14:14:43 2015
New Revision: 235624

URL: http://llvm.org/viewvc/llvm-project?rev=235624&view=rev
Log:
Merging r229227:

------------------------------------------------------------------------
r229227 | Matthew.Arsenault | 2015-02-13 21:55:57 -0500 (Fri, 13 Feb 2015) | 2 lines

R600/SI: Fix phys reg copies in SIFoldOperands

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/SIFoldOperands.cpp

Modified: llvm/branches/release_36/lib/Target/R600/SIFoldOperands.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIFoldOperands.cpp?rev=235624&r1=235623&r2=235624&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIFoldOperands.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIFoldOperands.cpp Thu Apr 23 14:14:43 2015
@@ -209,7 +209,12 @@ bool SIFoldOperands::runOnMachineFunctio
         APInt Imm;
 
         if (FoldingImm) {
-          const TargetRegisterClass *UseRC = MRI.getRegClass(UseOp.getReg());
+          unsigned UseReg = UseOp.getReg();
+          const TargetRegisterClass *UseRC
+            = TargetRegisterInfo::isVirtualRegister(UseReg) ?
+            MRI.getRegClass(UseReg) :
+            TRI.getRegClass(UseReg);
+
           Imm = APInt(64, OpToFold.getImm());
 
           // Split 64-bit constants into 32-bits for folding.
@@ -228,8 +233,13 @@ bool SIFoldOperands::runOnMachineFunctio
           // In order to fold immediates into copies, we need to change the
           // copy to a MOV.
           if (UseMI->getOpcode() == AMDGPU::COPY) {
-            unsigned MovOp = TII->getMovOpcode(
-                MRI.getRegClass(UseMI->getOperand(0).getReg()));
+            unsigned DestReg = UseMI->getOperand(0).getReg();
+            const TargetRegisterClass *DestRC
+              = TargetRegisterInfo::isVirtualRegister(DestReg) ?
+              MRI.getRegClass(DestReg) :
+              TRI.getRegClass(DestReg);
+
+            unsigned MovOp = TII->getMovOpcode(DestRC);
             if (MovOp == AMDGPU::COPY)
               continue;