[llvm-branch-commits] [llvm-branch] r235548 - Merging r228373:

[Tom Stellard]

Author: tstellar
Date: Wed Apr 22 16:13:09 2015
New Revision: 235548

URL: http://llvm.org/viewvc/llvm-project?rev=235548&view=rev
Log:
Merging r228373:

------------------------------------------------------------------------
r228373 | michel.daenzer | 2015-02-05 21:51:25 -0500 (Thu, 05 Feb 2015) | 8 lines

R600/SI: Don't enable WQM for V_INTERP_* instructions v2

Doesn't seem necessary anymore. I think this was mostly compensating for
not enabling WQM for texture sampling instructions.

v2: Add test coverage
Reviewed-by: Tom Stellard <tom at stellard.net>

------------------------------------------------------------------------

Added:
    llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.ll
Removed:
    llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
Modified:
    llvm/branches/release_36/lib/Target/R600/SILowerControlFlow.cpp

Modified: llvm/branches/release_36/lib/Target/R600/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SILowerControlFlow.cpp?rev=235548&r1=235547&r2=235548&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SILowerControlFlow.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SILowerControlFlow.cpp Wed Apr 22 16:13:09 2015
@@ -513,12 +513,6 @@ bool SILowerControlFlowPass::runOnMachin
         case AMDGPU::SI_INDIRECT_DST_V16:
           IndirectDst(MI);
           break;
-
-        case AMDGPU::V_INTERP_P1_F32:
-        case AMDGPU::V_INTERP_P2_F32:
-        case AMDGPU::V_INTERP_MOV_F32:
-          NeedWQM = true;
-          break;
       }
     }
   }

Removed: llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll?rev=235547&view=auto
==============================================================================
--- llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll (original)
+++ llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll (removed)
@@ -1,22 +0,0 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
-
-;CHECK: s_mov_b32
-;CHECK-NEXT: v_interp_mov_f32
-
-define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" {
-main_body:
-  %4 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
-  %5 = call i32 @llvm.SI.packf16(float %4, float %4)
-  %6 = bitcast i32 %5 to float
-  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %6, float %6, float %6, float %6)
-  ret void
-}
-
-declare void @llvm.AMDGPU.shader.type(i32)
-
-declare float @llvm.SI.fs.constant(i32, i32, i32) readnone
-
-declare i32 @llvm.SI.packf16(float, float) readnone
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

Added: llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.ll?rev=235548&view=auto
==============================================================================
--- llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.ll (added)
+++ llvm/branches/release_36/test/CodeGen/R600/llvm.SI.fs.interp.ll Wed Apr 22 16:13:09 2015
@@ -0,0 +1,30 @@
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
+
+;CHECK-NOT: s_wqm
+;CHECK: s_mov_b32
+;CHECK: v_interp_p1_f32
+;CHECK: v_interp_p2_f32
+;CHECK: v_interp_mov_f32
+
+define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 {
+main_body:
+  %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
+  %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4)
+  %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4)
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7)
+  ret void
+}
+
+declare void @llvm.AMDGPU.shader.type(i32)
+
+; Function Attrs: nounwind readnone
+declare float @llvm.SI.fs.constant(i32, i32, i32) #1
+
+; Function Attrs: nounwind readnone
+declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" }
+attributes #1 = { nounwind readnone }