[llvm-branch-commits] [llvm-branch] r213746 - Merging r213653:
Daniel Sanders
daniel.sanders at imgtec.com
Wed Jul 23 05:45:33 PDT 2014
Author: dsanders
Date: Wed Jul 23 07:45:33 2014
New Revision: 213746
URL: http://llvm.org/viewvc/llvm-project?rev=213746&view=rev
Log:
Merging r213653:
------------------------------------------------------------------------
r213653 | sstankovic | 2014-07-22 14:36:02 +0100 (Tue, 22 Jul 2014) | 7 lines
[mips] Fix two patterns that select i32's (for MIPS32r6) / i64's (for MIPS64r6)
from setne comparison with an i32.
The patterns that are fixed:
* (select (i32 (setne i32, immZExt16)), i32, i32) (for MIPS32r6)
* (select (i32 (setne i32, immZExt16)), i64, i64) (for MIPS64r6)
------------------------------------------------------------------------
Modified:
llvm/branches/release_35/ (props changed)
llvm/branches/release_35/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/branches/release_35/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/branches/release_35/test/CodeGen/Mips/cmov.ll
Propchange: llvm/branches/release_35/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jul 23 07:45:33 2014
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241
+/llvm/trunk:155241,213653
Modified: llvm/branches/release_35/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/Mips32r6InstrInfo.td?rev=213746&r1=213745&r2=213746&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/branches/release_35/lib/Target/Mips/Mips32r6InstrInfo.td Wed Jul 23 07:45:33 2014
@@ -796,8 +796,8 @@ def : MipsPat<(select (i32 (seteq i32:$c
(SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
ISA_MIPS32R6;
def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
- (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
- (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
+ (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
+ (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
ISA_MIPS32R6;
def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
i32:$f),
Modified: llvm/branches/release_35/lib/Target/Mips/Mips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/Mips64r6InstrInfo.td?rev=213746&r1=213745&r2=213746&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/Mips/Mips64r6InstrInfo.td (original)
+++ llvm/branches/release_35/lib/Target/Mips/Mips64r6InstrInfo.td Wed Jul 23 07:45:33 2014
@@ -191,9 +191,9 @@ def : MipsPat<(select (i32 (seteq i32:$c
immZExt16:$imm))))>,
ISA_MIPS64R6;
def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
- (OR64 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
+ (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
immZExt16:$imm))),
- (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
+ (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
immZExt16:$imm))))>,
ISA_MIPS64R6;
Modified: llvm/branches/release_35/test/CodeGen/Mips/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/cmov.ll?rev=213746&r1=213745&r2=213746&view=diff
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/cmov.ll (original)
+++ llvm/branches/release_35/test/CodeGen/Mips/cmov.ll Wed Jul 23 07:45:33 2014
@@ -116,6 +116,39 @@ entry:
ret i32 %cond
}
+; ALL-LABEL: cmov3_ne:
+
+; We won't check the result register since we can't know if the move is first
+; or last. We do know it will be either one of two registers so we can at least
+; check that.
+
+; FIXME: Use xori instead of addiu+xor.
+; 32-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
+; 32-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]
+; 32-CMOV: movn ${{[26]}}, $5, $[[R1]]
+
+; 32-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234
+; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]]
+; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[CC]]
+; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]
+
+; FIXME: Use xori instead of addiu+xor.
+; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
+; 64-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]
+; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
+
+; 64-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234
+; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]]
+; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[CC]]
+; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
+
+define i32 @cmov3_ne(i32 %a, i32 %b, i32 %c) nounwind readnone {
+entry:
+ %cmp = icmp ne i32 %a, 234
+ %cond = select i1 %cmp, i32 %b, i32 %c
+ ret i32 %cond
+}
+
; ALL-LABEL: cmov4:
; We won't check the result register since we can't know if the move is first
@@ -152,6 +185,47 @@ entry:
%cond = select i1 %cmp, i64 %b, i64 %c
ret i64 %cond
}
+
+; ALL-LABEL: cmov4_ne:
+
+; We won't check the result register since we can't know if the move is first
+; or last. We do know it will be one of two registers so we can at least check
+; that.
+
+; FIXME: Use xori instead of addiu+xor.
+; 32-CMOV-DAG: addiu $[[R0:[0-9]+]], $zero, 234
+; 32-CMOV-DAG: xor $[[R1:[0-9]+]], $4, $[[R0]]
+; 32-CMOV-DAG: lw $[[R2:2]], 16($sp)
+; 32-CMOV-DAG: lw $[[R3:3]], 20($sp)
+; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]]
+; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]]
+
+; 32-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234
+; 32-CMP-DAG: lw $[[R1:[0-9]+]], 16($sp)
+; 32-CMP-DAG: lw $[[R2:[0-9]+]], 20($sp)
+; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $6, $[[R0]]
+; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $7, $[[R0]]
+; 32-CMP-DAG: seleqz $[[T2:[0-9]+]], $[[R1]], $[[R0]]
+; 32-CMP-DAG: seleqz $[[T3:[0-9]+]], $[[R2]], $[[R0]]
+; 32-CMP-DAG: or $2, $[[T0]], $[[T2]]
+; 32-CMP-DAG: or $3, $[[T1]], $[[T3]]
+
+; FIXME: Use xori instead of addiu+xor.
+; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
+; 64-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]
+; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
+
+; 64-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234
+; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[R0]]
+; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[R0]]
+; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
+
+define i64 @cmov4_ne(i32 %a, i64 %b, i64 %c) nounwind readnone {
+entry:
+ %cmp = icmp ne i32 %a, 234
+ %cond = select i1 %cmp, i64 %b, i64 %c
+ ret i64 %cond
+}
; slti and conditional move.
;
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