[llvm-branch-commits] [llvm-branch] r195998 - Merging r195878:

[Bill Wendling]

Author: void
Date: Sat Nov 30 21:13:21 2013
New Revision: 195998

URL: http://llvm.org/viewvc/llvm-project?rev=195998&view=rev
Log:
Merging r195878:
------------------------------------------------------------------------
r195878 | tstellar | 2013-11-27 13:23:20 -0800 (Wed, 27 Nov 2013) | 3 lines

R600: Add support for ISD::FROUND

NOTE: This is a candidate for the 3.4 branch.
------------------------------------------------------------------------

Added:
    llvm/branches/release_34/test/CodeGen/R600/llvm.round.ll
      - copied unchanged from r195878, llvm/trunk/test/CodeGen/R600/llvm.round.ll
Modified:
    llvm/branches/release_34/   (props changed)
    llvm/branches/release_34/lib/Target/R600/AMDGPUISelLowering.cpp
    llvm/branches/release_34/lib/Target/R600/AMDGPUInstrInfo.td
    llvm/branches/release_34/lib/Target/R600/R600Instructions.td

Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Nov 30 21:13:21 2013
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195591,195599,195632,195635-195636,195670,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195798,195803,195812,195827,195834,195843,195887
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195591,195599,195632,195635-195636,195670,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195798,195803,195812,195827,195834,195843,195878,195887

Modified: llvm/branches/release_34/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/R600/AMDGPUISelLowering.cpp?rev=195998&r1=195997&r2=195998&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/branches/release_34/lib/Target/R600/AMDGPUISelLowering.cpp Sat Nov 30 21:13:21 2013
@@ -58,6 +58,7 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri
   setOperationAction(ISD::FABS,   MVT::f32, Legal);
   setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
+  setOperationAction(ISD::FROUND, MVT::f32, Legal);
 
   // The hardware supports ROTR, but not ROTL
   setOperationAction(ISD::ROTL, MVT::i32, Expand);

Modified: llvm/branches/release_34/lib/Target/R600/AMDGPUInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/R600/AMDGPUInstrInfo.td?rev=195998&r1=195997&r2=195998&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/R600/AMDGPUInstrInfo.td (original)
+++ llvm/branches/release_34/lib/Target/R600/AMDGPUInstrInfo.td Sat Nov 30 21:13:21 2013
@@ -83,3 +83,6 @@ def AMDGPUregister_store : SDNode<"AMDGP
 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
                         SDTypeProfile<0, 2, []>,
                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+
+def AMDGPUround : SDNode<"ISD::FROUND",
+                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;

Modified: llvm/branches/release_34/lib/Target/R600/R600Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/R600/R600Instructions.td?rev=195998&r1=195997&r2=195998&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/R600/R600Instructions.td (original)
+++ llvm/branches/release_34/lib/Target/R600/R600Instructions.td Sat Nov 30 21:13:21 2013
@@ -1110,6 +1110,10 @@ class COS_Common <bits<11> inst> : R600_
   let Itinerary = TransALU;
 }
 
+def CLAMP_R600 :  CLAMP <R600_Reg32>;
+def FABS_R600 : FABS<R600_Reg32>;
+def FNEG_R600 : FNEG<R600_Reg32>;
+
 //===----------------------------------------------------------------------===//
 // Helper patterns for complex intrinsics
 //===----------------------------------------------------------------------===//
@@ -1132,6 +1136,13 @@ class TGSI_LIT_Z_Common <InstR600 mul_li
   (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
 >;
 
+// FROUND pattern
+class FROUNDPat<Instruction CNDGE> : Pat <
+  (AMDGPUround f32:$x),
+  (CNDGE (ADD (FNEG_R600 (f32 HALF)), (FRACT $x)), (CEIL $x), (FLOOR $x))
+>;
+
+
 //===----------------------------------------------------------------------===//
 // R600 / R700 Instructions
 //===----------------------------------------------------------------------===//
@@ -1173,6 +1184,7 @@ let Predicates = [isR600] in {
   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 
   def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
+  def : FROUNDPat <CNDGE_r600>;
 
   def R600_ExportSwz : ExportSwzInst {
     let Word1{20-17} = 0; // BURST_COUNT
@@ -1726,6 +1738,8 @@ def LDS_USHORT_READ_RET : R600_LDS_1A <0
   // SHA-256 Patterns
   def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
 
+  def : FROUNDPat <CNDGE_eg>;
+
   def EG_ExportSwz : ExportSwzInst {
     let Word1{19-16} = 0; // BURST_COUNT
     let Word1{20} = 0; // VALID_PIXEL_MODE
@@ -2090,10 +2104,6 @@ def TXD_SHADOW: InstR600 <
 } // End isPseudo = 1
 } // End usesCustomInserter = 1
 
-def CLAMP_R600 :  CLAMP <R600_Reg32>;
-def FABS_R600 : FABS<R600_Reg32>;
-def FNEG_R600 : FNEG<R600_Reg32>;
-
 //===---------------------------------------------------------------------===//
 // Return instruction
 //===---------------------------------------------------------------------===//