[llvm-branch-commits] [llvm-branch] r195870 - Merging r195576:
Bill Wendling
isanbard at gmail.com
Wed Nov 27 11:40:37 PST 2013
Author: void
Date: Wed Nov 27 13:40:37 2013
New Revision: 195870
URL: http://llvm.org/viewvc/llvm-project?rev=195870&view=rev
Log:
Merging r195576:
------------------------------------------------------------------------
r195576 | venkatra | 2013-11-24 12:23:25 -0800 (Sun, 24 Nov 2013) | 2 lines
[Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64.
------------------------------------------------------------------------
Modified:
llvm/branches/release_34/ (props changed)
llvm/branches/release_34/lib/Target/Sparc/Sparc.h
llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.cpp
llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.h
llvm/branches/release_34/lib/Target/Sparc/SparcRegisterInfo.cpp
llvm/branches/release_34/test/CodeGen/SPARC/64abi.ll
Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Nov 27 13:40:37 2013
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195575,195591,195599,195632,195635-195636,195670,195679,195682,195684,195713,195716,195769,195773,195779,195791,195798
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195591,195599,195632,195635-195636,195670,195679,195682,195684,195713,195716,195769,195773,195779,195791,195798
Modified: llvm/branches/release_34/lib/Target/Sparc/Sparc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/Sparc/Sparc.h?rev=195870&r1=195869&r2=195870&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/Sparc/Sparc.h (original)
+++ llvm/branches/release_34/lib/Target/Sparc/Sparc.h Wed Nov 27 13:40:37 2013
@@ -105,5 +105,22 @@ namespace llvm {
}
llvm_unreachable("Invalid cond code");
}
+
+ inline static unsigned HI22(int64_t imm) {
+ return (unsigned)((imm >> 10) & ((1 << 22)-1));
+ }
+
+ inline static unsigned LO10(int64_t imm) {
+ return (unsigned)(imm & 0x3FF);
+ }
+
+ inline static unsigned HIX22(int64_t imm) {
+ return HI22(~imm);
+ }
+
+ inline static unsigned LOX10(int64_t imm) {
+ return ~LO10(~imm);
+ }
+
} // end namespace llvm
#endif
Modified: llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.cpp?rev=195870&r1=195869&r2=195870&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.cpp (original)
+++ llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.cpp Wed Nov 27 13:40:37 2013
@@ -33,6 +33,51 @@ DisableLeafProc("disable-sparc-leaf-proc
cl::Hidden);
+void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ int NumBytes,
+ unsigned ADDrr,
+ unsigned ADDri) const {
+
+ DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
+ const SparcInstrInfo &TII =
+ *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
+
+ if (NumBytes >= -4096 && NumBytes < 4096) {
+ BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
+ .addReg(SP::O6).addImm(NumBytes);
+ return;
+ }
+
+ // Emit this the hard way. This clobbers G1 which we always know is
+ // available here.
+ if (NumBytes >= 0) {
+ // Emit nonnegative numbers with sethi + or.
+ // sethi %hi(NumBytes), %g1
+ // or %g1, %lo(NumBytes), %g1
+ // add %sp, %g1, %sp
+ BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
+ .addImm(HI22(NumBytes));
+ BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
+ .addReg(SP::G1).addImm(LO10(NumBytes));
+ BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
+ .addReg(SP::O6).addReg(SP::G1);
+ return ;
+ }
+
+ // Emit negative numbers with sethi + xor.
+ // sethi %hix(NumBytes), %g1
+ // xor %g1, %lox(NumBytes), %g1
+ // add %sp, %g1, %sp
+ BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
+ .addImm(HIX22(NumBytes));
+ BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
+ .addReg(SP::G1).addImm(LOX10(NumBytes));
+ BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
+ .addReg(SP::O6).addReg(SP::G1);
+}
+
void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
@@ -55,21 +100,8 @@ void SparcFrameLowering::emitPrologue(Ma
SAVErr = SP::ADDrr;
}
NumBytes = - SubTarget.getAdjustedFrameSize(NumBytes);
+ emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
- if (NumBytes >= -4096) {
- BuildMI(MBB, MBBI, dl, TII.get(SAVEri), SP::O6)
- .addReg(SP::O6).addImm(NumBytes);
- } else {
- // Emit this the hard way. This clobbers G1 which we always know is
- // available here.
- unsigned OffHi = (unsigned)NumBytes >> 10U;
- BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
- // Emit G1 = G1 + I6
- BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
- .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
- BuildMI(MBB, MBBI, dl, TII.get(SAVErr), SP::O6)
- .addReg(SP::O6).addReg(SP::G1);
- }
MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
@@ -100,11 +132,9 @@ eliminateCallFramePseudoInstr(MachineFun
int Size = MI.getOperand(0).getImm();
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
- const SparcInstrInfo &TII =
- *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
+
if (Size)
- BuildMI(MBB, I, DL, TII.get(SP::ADDri), SP::O6).addReg(SP::O6)
- .addImm(Size);
+ emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
}
MBB.erase(I);
}
@@ -131,21 +161,7 @@ void SparcFrameLowering::emitEpilogue(Ma
return;
NumBytes = SubTarget.getAdjustedFrameSize(NumBytes);
-
- if (NumBytes < 4096) {
- BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
- .addReg(SP::O6).addImm(NumBytes);
- } else {
- // Emit this the hard way. This clobbers G1 which we always know is
- // available here.
- unsigned OffHi = (unsigned)NumBytes >> 10U;
- BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
- // Emit G1 = G1 + I6
- BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
- .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
- BuildMI(MBB, MBBI, dl, TII.get(SP::ADDrr), SP::O6)
- .addReg(SP::O6).addReg(SP::G1);
- }
+ emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
}
bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
Modified: llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.h?rev=195870&r1=195869&r2=195870&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.h (original)
+++ llvm/branches/release_34/lib/Target/Sparc/SparcFrameLowering.h Wed Nov 27 13:40:37 2013
@@ -49,6 +49,14 @@ private:
// Returns true if MF is a leaf procedure.
bool isLeafProc(MachineFunction &MF) const;
+
+
+ // Emits code for adjusting SP in function prologue/epilogue.
+ void emitSPAdjustment(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ int NumBytes, unsigned ADDrr, unsigned ADDri) const;
+
};
} // End llvm namespace
Modified: llvm/branches/release_34/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=195870&r1=195869&r2=195870&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/branches/release_34/lib/Target/Sparc/SparcRegisterInfo.cpp Wed Nov 27 13:40:37 2013
@@ -105,19 +105,46 @@ static void replaceFI(MachineFunction &M
// encode it.
MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
- } else {
- // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
- // scavenge a register here instead of reserving G1 all of the time.
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
- unsigned OffHi = (unsigned)Offset >> 10U;
- BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
+ return;
+ }
+
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
+
+ // FIXME: it would be better to scavenge a register here instead of
+ // reserving G1 all of the time.
+ if (Offset >= 0) {
+ // Emit nonnegaive immediates with sethi + or.
+ // sethi %hi(Offset), %g1
+ // add %g1, %fp, %g1
+ // Insert G1+%lo(offset) into the user.
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
+ .addImm(HI22(Offset));
+
+
// Emit G1 = G1 + I6
BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
.addReg(FramePtr);
// Insert: G1+%lo(offset) into the user.
MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
- MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
+ MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
+ return;
}
+
+ // Emit Negative numbers with sethi + xor
+ // sethi %hix(Offset), %g1
+ // xor %g1, %lox(offset), %g1
+ // add %g1, %fp, %g1
+ // Insert: G1 + 0 into the user.
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
+ .addImm(HIX22(Offset));
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
+ .addReg(SP::G1).addImm(LOX10(Offset));
+
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
+ .addReg(FramePtr);
+ // Insert: G1+%lo(offset) into the user.
+ MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
+ MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
}
Modified: llvm/branches/release_34/test/CodeGen/SPARC/64abi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/SPARC/64abi.ll?rev=195870&r1=195869&r2=195870&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/SPARC/64abi.ll (original)
+++ llvm/branches/release_34/test/CodeGen/SPARC/64abi.ll Wed Nov 27 13:40:37 2013
@@ -390,3 +390,24 @@ entry:
%2 = add nsw i32 %0, %1
ret i32 %2
}
+
+; CHECK-LABEL: test_large_stack
+
+; CHECK: sethi 16, %g1
+; CHECK: xor %g1, -176, %g1
+; CHECK: save %sp, %g1, %sp
+
+; CHECK: sethi 14, %g1
+; CHECK: xor %g1, -1, %g1
+; CHECK: add %g1, %fp, %g1
+; CHECK: call use_buf
+
+define i32 @test_large_stack() {
+entry:
+ %buffer1 = alloca [16384 x i8], align 8
+ %buffer1.sub = getelementptr inbounds [16384 x i8]* %buffer1, i32 0, i32 0
+ %0 = call i32 @use_buf(i32 16384, i8* %buffer1.sub)
+ ret i32 %0
+}
+
+declare i32 @use_buf(i32, i8*)
More information about the llvm-branch-commits
mailing list