[llvm-branch-commits] [llvm-branch] r182829 - Merging r182394:
Bill Wendling
isanbard at gmail.com
Tue May 28 23:56:17 PDT 2013
Author: void
Date: Wed May 29 01:56:17 2013
New Revision: 182829
URL: http://llvm.org/viewvc/llvm-project?rev=182829&view=rev
Log:
Merging r182394:
------------------------------------------------------------------------
r182394 | jholewinski | 2013-05-21 09:51:30 -0700 (Tue, 21 May 2013) | 1 line
[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic
------------------------------------------------------------------------
Modified:
llvm/branches/release_33/ (props changed)
llvm/branches/release_33/include/llvm/IR/IntrinsicsNVVM.td
llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
llvm/branches/release_33/lib/Target/NVPTX/NVPTXInstrInfo.td
llvm/branches/release_33/lib/Target/NVPTX/NVPTXIntrinsics.td
llvm/branches/release_33/test/CodeGen/NVPTX/intrinsics.ll
Propchange: llvm/branches/release_33/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed May 29 01:56:17 2013
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,181286,181296,181313,181363,181366,181397,181423,181450,181524,181529,181540,181576-181580,181586,181600,181678,181706,181792,181800,181842,181864,182072,182112-182113,182253-182254,182297-182298,182344,182364,182385,182387,182485-182486,182656
+/llvm/trunk:155241,181286,181296,181313,181363,181366,181397,181423,181450,181524,181529,181540,181576-181580,181586,181600,181678,181706,181792,181800,181842,181864,182072,182112-182113,182253-182254,182297-182298,182344,182364,182385,182387,182394,182485-182486,182656
Modified: llvm/branches/release_33/include/llvm/IR/IntrinsicsNVVM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_33/include/llvm/IR/IntrinsicsNVVM.td?rev=182829&r1=182828&r2=182829&view=diff
==============================================================================
--- llvm/branches/release_33/include/llvm/IR/IntrinsicsNVVM.td (original)
+++ llvm/branches/release_33/include/llvm/IR/IntrinsicsNVVM.td Wed May 29 01:56:17 2013
@@ -405,6 +405,8 @@ def llvm_anyi64ptr_ty : LLVMAnyPoint
// Sqrt
//
+ def int_nvvm_sqrt_f : GCCBuiltin<"__nvvm_sqrt_f">,
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
def int_nvvm_sqrt_rn_ftz_f : GCCBuiltin<"__nvvm_sqrt_rn_ftz_f">,
Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
def int_nvvm_sqrt_rn_f : GCCBuiltin<"__nvvm_sqrt_rn_f">,
Modified: llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp?rev=182829&r1=182828&r2=182829&view=diff
==============================================================================
--- llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp (original)
+++ llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp Wed May 29 01:56:17 2013
@@ -42,6 +42,11 @@ static cl::opt<int> UsePrecDivF32(
" IEEE Compliant F32 div.rnd if avaiable."),
cl::init(2));
+static cl::opt<bool>
+UsePrecSqrtF32("nvptx-prec-sqrtf32",
+ cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
+ cl::init(true));
+
/// createNVPTXISelDag - This pass converts a legalized DAG into a
/// NVPTX-specific DAG, ready for instruction scheduling.
FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
@@ -74,6 +79,8 @@ NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVP
// Decide how to translate f32 div
do_DIVF32_PREC = UsePrecDivF32;
+ // Decide how to translate f32 sqrt
+ do_SQRTF32_PREC = UsePrecSqrtF32;
// sm less than sm_20 does not support div.rnd. Use div.full.
if (do_DIVF32_PREC == 2 && !Subtarget.reqPTX20())
do_DIVF32_PREC = 1;
Modified: llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.h?rev=182829&r1=182828&r2=182829&view=diff
==============================================================================
--- llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.h (original)
+++ llvm/branches/release_33/lib/Target/NVPTX/NVPTXISelDAGToDAG.h Wed May 29 01:56:17 2013
@@ -41,6 +41,10 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGTo
// Otherwise, use div.full
int do_DIVF32_PREC;
+ // If true, generate sqrt.rn, else generate sqrt.approx. If FTZ
+ // is true, then generate the corresponding FTZ version.
+ bool do_SQRTF32_PREC;
+
// If true, add .ftz to f32 instructions.
// This is only meaningful for sm_20 and later, as the default
// is not ftz.
Modified: llvm/branches/release_33/lib/Target/NVPTX/NVPTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_33/lib/Target/NVPTX/NVPTXInstrInfo.td?rev=182829&r1=182828&r2=182829&view=diff
==============================================================================
--- llvm/branches/release_33/lib/Target/NVPTX/NVPTXInstrInfo.td (original)
+++ llvm/branches/release_33/lib/Target/NVPTX/NVPTXInstrInfo.td Wed May 29 01:56:17 2013
@@ -75,6 +75,9 @@ def allowFMA_ftz : Predicate<"(allowFMA
def do_DIVF32_APPROX : Predicate<"do_DIVF32_PREC==0">;
def do_DIVF32_FULL : Predicate<"do_DIVF32_PREC==1">;
+def do_SQRTF32_APPROX : Predicate<"do_SQRTF32_PREC==0">;
+def do_SQRTF32_RN : Predicate<"do_SQRTF32_PREC==1">;
+
def hasHWROT32 : Predicate<"Subtarget.hasHWROT32()">;
def true : Predicate<"1">;
Modified: llvm/branches/release_33/lib/Target/NVPTX/NVPTXIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_33/lib/Target/NVPTX/NVPTXIntrinsics.td?rev=182829&r1=182828&r2=182829&view=diff
==============================================================================
--- llvm/branches/release_33/lib/Target/NVPTX/NVPTXIntrinsics.td (original)
+++ llvm/branches/release_33/lib/Target/NVPTX/NVPTXIntrinsics.td Wed May 29 01:56:17 2013
@@ -512,6 +512,16 @@ def INT_NVVM_SQRT_RM_D : F_MATH_1<"sqrt.
def INT_NVVM_SQRT_RP_D : F_MATH_1<"sqrt.rp.f64 \t$dst, $src0;", Float64Regs,
Float64Regs, int_nvvm_sqrt_rp_d>;
+// nvvm_sqrt intrinsic
+def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
+ (INT_NVVM_SQRT_RN_FTZ_F Float32Regs:$a)>, Requires<[doF32FTZ, do_SQRTF32_RN]>;
+def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
+ (INT_NVVM_SQRT_RN_F Float32Regs:$a)>, Requires<[do_SQRTF32_RN]>;
+def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
+ (INT_NVVM_SQRT_APPROX_FTZ_F Float32Regs:$a)>, Requires<[doF32FTZ]>;
+def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
+ (INT_NVVM_SQRT_APPROX_F Float32Regs:$a)>;
+
//
// Rsqrt
//
Modified: llvm/branches/release_33/test/CodeGen/NVPTX/intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_33/test/CodeGen/NVPTX/intrinsics.ll?rev=182829&r1=182828&r2=182829&view=diff
==============================================================================
--- llvm/branches/release_33/test/CodeGen/NVPTX/intrinsics.ll (original)
+++ llvm/branches/release_33/test/CodeGen/NVPTX/intrinsics.ll Wed May 29 01:56:17 2013
@@ -15,5 +15,12 @@ define ptx_device double @test_fabs(doub
ret double %x
}
+define float @test_nvvm_sqrt(float %a) {
+ %val = call float @llvm.nvvm.sqrt.f(float %a)
+ ret float %val
+}
+
+
declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)
+declare float @llvm.nvvm.sqrt.f(float)
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