[llvm-branch-commits] [llvm-tag] r183416 - Add 3.3 release notes for PowerPC.

Bill Schmidt wschmidt at linux.vnet.ibm.com
Thu Jun 6 07:28:22 PDT 2013

Author: wschmidt
Date: Thu Jun  6 09:27:30 2013
New Revision: 183416

URL: http://llvm.org/viewvc/llvm-project?rev=183416&view=rev
Add 3.3 release notes for PowerPC.


Modified: llvm/tags/RELEASE_33/rc3/docs/ReleaseNotes.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/tags/RELEASE_33/rc3/docs/ReleaseNotes.rst?rev=183416&r1=183415&r2=183416&view=diff
--- llvm/tags/RELEASE_33/rc3/docs/ReleaseNotes.rst (original)
+++ llvm/tags/RELEASE_33/rc3/docs/ReleaseNotes.rst Thu Jun  6 09:27:30 2013
@@ -103,6 +103,30 @@ Hexagon Target
   architectures which are no longer in use. Currently supported
   architectures are hexagonv4 and hexagonv5.
+PowerPC Target
+New features and improvements:
+- PowerPC now supports an assembly parser.
+- Support added for thread-local storage.  64-bit ELF subtarget only.
+- Support added for medium and large code model (-mcmodel=medium,large).
+  Medium code model is now the default.  64-bit ELF subtarget only.
+- Improved register allocation (fewer reserved registers).
+- 64-bit atomic load and store are now supported.
+- Improved code generation for unaligned memory accesses of scalar types.
+- Improved performance of floating-point divide and square root
+  with -ffast-math.
+- Support for predicated returns.
+- Improved code generation for comparisons.
+- Support added for inline setjmp and longjmp.
+- Support added for many instructions introduced in PowerISA 2.04, 2.05,
+  and 2.06.
+- Improved spill code for vector registers.
+- Support added for -mno-altivec.
+- ABI compatibility fixes for complex parameters, 128-bit integer parameters,
+  and varargs functions.  64-bit ELF subtarget only.
 Loop Vectorizer

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