[llvm-branch-commits] [llvm-branch] r197779 - Merging r197492:
Bill Wendling
isanbard at gmail.com
Thu Dec 19 20:29:56 PST 2013
Author: void
Date: Thu Dec 19 22:29:56 2013
New Revision: 197779
URL: http://llvm.org/viewvc/llvm-project?rev=197779&view=rev
Log:
Merging r197492:
------------------------------------------------------------------------
r197492 | dyatkovskiy | 2013-12-17 04:07:33 -0800 (Tue, 17 Dec 2013) | 26 lines
Fix for PR18045:
http://llvm.org/bugs/show_bug.cgi?id=18045
Short issue description:
For X86 machines with sse < sse4.1 we got failures for some
particular load/store vector sequences:
$ clang-trunk -m32 -O2 test-case.c
fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850,
0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82]
[ID=58]
0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43]
0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23]
0x41dcb10: i32 = undef [ID=2]
The reason is that EltsFromConsecutiveLoads could emit such load instruction
both before and after legalize stage. Though this instruction is not legal for
machines with SSSE3 and lower.
The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we
check whether nodes it emits are legal.
P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8),
perhaps I'll slow with response, so you better reject this commit. Thanks!
------------------------------------------------------------------------
Added:
llvm/branches/release_34/test/CodeGen/X86/v4i32load-crash.ll
- copied unchanged from r197492, llvm/trunk/test/CodeGen/X86/v4i32load-crash.ll
Modified:
llvm/branches/release_34/ (props changed)
llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp
Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Dec 19 22:29:56 2013
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195411,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195495,195504-195505,195514,195528,195535,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195710,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196144,196151,196153,196156,196158,196172,196189-196192,196198-196199,196208-196211,196261,196267,196269,196294,196359-196362,196369,196391,196456,196493,196508,196532-196533,196535,196538,196588,196611-196612,196637-196638,196658,196668,196725,196735,196!
751,19675
5,196768,196806,196858,197047,197089,197178,197215-197216,197228,197449,197718
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195411,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195495,195504-195505,195514,195528,195535,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195710,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196144,196151,196153,196156,196158,196172,196189-196192,196198-196199,196208-196211,196261,196267,196269,196294,196359-196362,196369,196391,196456,196493,196508,196532-196533,196535,196538,196588,196611-196612,196637-196638,196658,196668,196725,196735,196!
751,19675
5,196768,196806,196858,197047,197089,197178,197215-197216,197228,197449,197492,197718
Modified: llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp?rev=197779&r1=197778&r2=197779&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp Thu Dec 19 22:29:56 2013
@@ -5395,7 +5395,8 @@ LowerAsSplatVectorLoad(SDValue SrcOp, MV
/// rather than undef via VZEXT_LOAD, but we do not detect that case today.
/// There's even a handy isZeroNode for that purpose.
static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
- SDLoc &DL, SelectionDAG &DAG) {
+ SDLoc &DL, SelectionDAG &DAG,
+ bool isAfterLegalize) {
EVT EltVT = VT.getVectorElementType();
unsigned NumElems = Elts.size();
@@ -5431,7 +5432,13 @@ static SDValue EltsFromConsecutiveLoads(
// load of the entire vector width starting at the base pointer. If we found
// consecutive loads for the low half, generate a vzext_load node.
if (LastLoadedElt == NumElems - 1) {
+
+ if (isAfterLegalize &&
+ !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
+ return SDValue();
+
SDValue NewLd = SDValue();
+
if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
LDBase->getPointerInfo(),
@@ -6075,7 +6082,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDV
V[i] = Op.getOperand(i);
// Check for elements which are consecutive loads.
- SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
+ SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
if (LD.getNode())
return LD;
@@ -16263,7 +16270,7 @@ static SDValue PerformShuffleCombine(SDN
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
- return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
+ return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
}
/// PerformTruncateCombine - Converts truncate operation to
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