[llvm-branch-commits] [llvm-branch] r197325 - Add release notes for the PowerPC backend

[Hal Finkel]

Author: hfinkel
Date: Sat Dec 14 08:41:55 2013
New Revision: 197325

URL: http://llvm.org/viewvc/llvm-project?rev=197325&view=rev
Log:
Add release notes for the PowerPC backend

Modified:
    llvm/branches/release_34/docs/ReleaseNotes.rst

Modified: llvm/branches/release_34/docs/ReleaseNotes.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/docs/ReleaseNotes.rst?rev=197325&r1=197324&r2=197325&view=diff
==============================================================================
--- llvm/branches/release_34/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_34/docs/ReleaseNotes.rst Sat Dec 14 08:41:55 2013
@@ -110,6 +110,22 @@ For more information on MSA (including d
 see the `MIPS SIMD page at Imagination Technologies
 <http://imgtec.com/mips/mips-simd.asp>`_
 
+PowerPC Target
+--------------
+
+Changes in the PowerPC backend include:
+
+* fast-isel support (for faster -O0 code generation)
+* many improvements to the builtin assembler
+* support for generating unaligned (Altivec) vector loads
+* support for generating the fcpsgn instruction
+* generate frin for round() (not nearbyint() and rint(), which had been done only in fast-math mode)
+* improved instruction scheduling for embedded cores (such as the A2)
+* improved prologue/epilogue generation (especially in 32-bit mode)
+* support for dynamic stack alignment (and dynamic stack allocations with large alignments)
+* improved generation of counter-register-based loops
+* bug fixes
+
 SPARC Target
 ------------