[llvm-branch-commits] [llvm-branch] r196704 - Merging r196588:
Bill Wendling
isanbard at gmail.com
Sat Dec 7 16:17:29 PST 2013
Author: void
Date: Sat Dec 7 18:17:29 2013
New Revision: 196704
URL: http://llvm.org/viewvc/llvm-project?rev=196704&view=rev
Log:
Merging r196588:
------------------------------------------------------------------------
r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines
Bug 18149: [AArch32] VSel instructions has no ARMCC field
The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.
------------------------------------------------------------------------
Modified:
llvm/branches/release_34/ (props changed)
llvm/branches/release_34/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/release_34/test/CodeGen/ARM/sub-cmp-peephole.ll
Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Dec 7 18:17:29 2013
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196151,196153,196189-196192,196198-196199,196208-196209,196211,196261,196267,196269,196294,196359-196362,196369,196391,196456,196508,196532-196533,196535,196538,196611,196638,196658
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196151,196153,196189-196192,196198-196199,196208-196209,196211,196261,196267,196269,196294,196359-196362,196369,196391,196456,196508,196532-196533,196535,196538,196588,196611,196638,196658
Modified: llvm/branches/release_34/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=196704&r1=196703&r2=196704&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/release_34/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Dec 7 18:17:29 2013
@@ -2372,8 +2372,32 @@ optimizeCompareInstr(MachineInstr *CmpIn
isSafe = true;
break;
}
- // Condition code is after the operand before CPSR.
- ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
+ // Condition code is after the operand before CPSR except for VSELs.
+ ARMCC::CondCodes CC;
+ bool IsInstrVSel = true;
+ switch (Instr.getOpcode()) {
+ default:
+ IsInstrVSel = false;
+ CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
+ break;
+ case ARM::VSELEQD:
+ case ARM::VSELEQS:
+ CC = ARMCC::EQ;
+ break;
+ case ARM::VSELGTD:
+ case ARM::VSELGTS:
+ CC = ARMCC::GT;
+ break;
+ case ARM::VSELGED:
+ case ARM::VSELGES:
+ CC = ARMCC::GE;
+ break;
+ case ARM::VSELVSS:
+ case ARM::VSELVSD:
+ CC = ARMCC::VS;
+ break;
+ }
+
if (Sub) {
ARMCC::CondCodes NewCC = getSwappedCondition(CC);
if (NewCC == ARMCC::AL)
@@ -2384,11 +2408,14 @@ optimizeCompareInstr(MachineInstr *CmpIn
// If it is safe to remove CmpInstr, the condition code of these
// operands will be modified.
if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
- Sub->getOperand(2).getReg() == SrcReg)
- OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
- NewCC));
- }
- else
+ Sub->getOperand(2).getReg() == SrcReg) {
+ // VSel doesn't support condition code update.
+ if (IsInstrVSel)
+ return false;
+ OperandsToUpdate.push_back(
+ std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
+ }
+ } else
switch (CC) {
default:
// CPSR can be used multiple times, we should continue.
Modified: llvm/branches/release_34/test/CodeGen/ARM/sub-cmp-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/ARM/sub-cmp-peephole.ll?rev=196704&r1=196703&r2=196704&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/ARM/sub-cmp-peephole.ll (original)
+++ llvm/branches/release_34/test/CodeGen/ARM/sub-cmp-peephole.ll Sat Dec 7 18:17:29 2013
@@ -1,4 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8
+
define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry:
@@ -84,3 +87,60 @@ land.lhs.true:
if.end11: ; preds = %num2long.exit
ret i32 23
}
+
+define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
+entry:
+; CHECK-LABEL: float_sel:
+; CHECK-NOT: cmp
+; V8-LABEL: float_sel:
+; V8-NOT: cmp
+; V8: vseleq.f32
+ %sub = sub i32 %a, %b
+ %cmp = icmp eq i32 %sub, 0
+ %ret = select i1 %cmp, float %x, float %y
+ ret float %ret
+}
+
+define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
+entry:
+; CHECK-LABEL: double_sel:
+; CHECK-NOT: cmp
+; V8-LABEL: double_sel:
+; V8-NOT: cmp
+; V8: vseleq.f64
+ %sub = sub i32 %a, %b
+ %cmp = icmp eq i32 %sub, 0
+ %ret = select i1 %cmp, double %x, double %y
+ ret double %ret
+}
+
+ at t = common global i32 0
+define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
+entry:
+; CHECK-LABEL: double_sub:
+; CHECK: subs
+; CHECK-NOT: cmp
+; V8-LABEL: double_sub:
+; V8: vsel
+ %cmp = icmp sgt i32 %a, %b
+ %sub = sub i32 %a, %b
+ store i32 %sub, i32* @t
+ %ret = select i1 %cmp, double %x, double %y
+ ret double %ret
+}
+
+define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
+entry:
+; V7-LABEL: double_sub_swap:
+; V7-NOT: cmp
+; V7: subs
+; V8-LABEL: double_sub_swap:
+; V8-NOT: subs
+; V8: cmp
+; V8: vsel
+ %cmp = icmp sgt i32 %a, %b
+ %sub = sub i32 %b, %a
+ %ret = select i1 %cmp, double %x, double %y
+ store i32 %sub, i32* @t
+ ret double %ret
+}
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