[llvm-branch-commits] [cfe-branch] r196678 - Merging r196209:
Bill Wendling
isanbard at gmail.com
Sat Dec 7 16:02:12 PST 2013
Author: void
Date: Sat Dec 7 18:02:12 2013
New Revision: 196678
URL: http://llvm.org/viewvc/llvm-project?rev=196678&view=rev
Log:
Merging r196209:
------------------------------------------------------------------------
r196209 | haoliu | 2013-12-02 21:58:49 -0800 (Mon, 02 Dec 2013) | 3 lines
AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions.
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.
------------------------------------------------------------------------
Modified:
cfe/branches/release_34/ (props changed)
cfe/branches/release_34/include/clang/Basic/arm_neon.td
cfe/branches/release_34/test/CodeGen/aarch64-neon-intrinsics.c
Propchange: cfe/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Dec 7 18:02:12 2013
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:195126,195128,195135-195136,195146,195149,195154,195158,195163,195168,195174,195249,195268,195283,195303,195326,195329,195367,195384,195409,195420,195422,195501,195547,195556,195558,195587,195620,195635,195669,195687,195693,195710,195713,195716,195756,195760,195768,195777,195789,195792,195804,195827,195843-195844,195877,195887-195888,195897,195903,195905-195906,195932,195936-195943,195970,195983,196045,196048,196050,196058,196114-196115,196153,196189-196192,196198-196199,196206,196208,196215,196370,196387,196423,196454,196459,196488,196532,196538,196658
+/cfe/trunk:195126,195128,195135-195136,195146,195149,195154,195158,195163,195168,195174,195249,195268,195283,195303,195326,195329,195367,195384,195409,195420,195422,195501,195547,195556,195558,195587,195620,195635,195669,195687,195693,195710,195713,195716,195756,195760,195768,195777,195789,195792,195804,195827,195843-195844,195877,195887-195888,195897,195903,195905-195906,195932,195936-195943,195970,195983,196045,196048,196050,196058,196114-196115,196153,196189-196192,196198-196199,196206,196208-196209,196215,196370,196387,196423,196454,196459,196488,196532,196538,196658
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_34/include/clang/Basic/arm_neon.td
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_34/include/clang/Basic/arm_neon.td?rev=196678&r1=196677&r2=196678&view=diff
==============================================================================
--- cfe/branches/release_34/include/clang/Basic/arm_neon.td (original)
+++ cfe/branches/release_34/include/clang/Basic/arm_neon.td Sat Dec 7 18:02:12 2013
@@ -603,20 +603,22 @@ def LD4_DUP : WInst<"vld4_dup", "4c",
////////////////////////////////////////////////////////////////////////////////
// Addition
-// With additional Qd type.
-def ADD : IOpInst<"vadd", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd", OP_ADD>;
+// With additional d, Qd type.
+def ADD : IOpInst<"vadd", "ddd", "csilfdUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd",
+ OP_ADD>;
////////////////////////////////////////////////////////////////////////////////
// Subtraction
// With additional Qd type.
-def SUB : IOpInst<"vsub", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd", OP_SUB>;
+def SUB : IOpInst<"vsub", "ddd", "csildfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd",
+ OP_SUB>;
////////////////////////////////////////////////////////////////////////////////
// Multiplication
// With additional Qd type.
-def MUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MUL>;
-def MLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLA>;
-def MLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLS>;
+def MUL : IOpInst<"vmul", "ddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MUL>;
+def MLA : IOpInst<"vmla", "dddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLA>;
+def MLS : IOpInst<"vmls", "dddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLS>;
////////////////////////////////////////////////////////////////////////////////
// Multiplication Extended
@@ -624,13 +626,13 @@ def MULX : SInst<"vmulx", "ddd", "fdQfQd
////////////////////////////////////////////////////////////////////////////////
// Division
-def FDIV : IOpInst<"vdiv", "ddd", "fQfQd", OP_DIV>;
+def FDIV : IOpInst<"vdiv", "ddd", "fdQfQd", OP_DIV>;
////////////////////////////////////////////////////////////////////////////////
// Vector fused multiply-add operations
-// With additional Qd type.
-def FMLA : SInst<"vfma", "dddd", "fQfQd">;
-def FMLS : SInst<"vfms", "dddd", "fQfQd">;
+// With additional d, Qd type.
+def FMLA : SInst<"vfma", "dddd", "fdQfQd">;
+def FMLS : SInst<"vfms", "dddd", "fdQfQd">;
////////////////////////////////////////////////////////////////////////////////
// MUL, FMA, FMS definitions with scalar argument
@@ -647,14 +649,14 @@ def BSL : SInst<"vbsl", "dudd",
////////////////////////////////////////////////////////////////////////////////
// Absolute Difference
// With additional Qd type.
-def ABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">;
+def ABD : SInst<"vabd", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">;
////////////////////////////////////////////////////////////////////////////////
// saturating absolute/negate
// With additional Qd/Ql type.
-def ABS : SInst<"vabs", "dd", "csilfQcQsQiQfQlQd">;
+def ABS : SInst<"vabs", "dd", "csilfdQcQsQiQfQlQd">;
def QABS : SInst<"vqabs", "dd", "csilQcQsQiQl">;
-def NEG : SOpInst<"vneg", "dd", "csilfQcQsQiQfQdQl", OP_NEG>;
+def NEG : SOpInst<"vneg", "dd", "csilfdQcQsQiQfQdQl", OP_NEG>;
def QNEG : SInst<"vqneg", "dd", "csilQcQsQiQl">;
////////////////////////////////////////////////////////////////////////////////
@@ -756,13 +758,13 @@ def CMLT : SInst<"vcltz", "ud", "csifdQ
////////////////////////////////////////////////////////////////////////////////
// Max/Min Integer
// With additional Qd type.
-def MAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">;
-def MIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">;
+def MAX : SInst<"vmax", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">;
+def MIN : SInst<"vmin", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">;
////////////////////////////////////////////////////////////////////////////////
// MaxNum/MinNum Floating Point
-def FMAXNM : SInst<"vmaxnm", "ddd", "fQfQd">;
-def FMINNM : SInst<"vminnm", "ddd", "fQfQd">;
+def FMAXNM : SInst<"vmaxnm", "ddd", "fdQfQd">;
+def FMINNM : SInst<"vminnm", "ddd", "fdQfQd">;
////////////////////////////////////////////////////////////////////////////////
// Pairwise Max/Min
Modified: cfe/branches/release_34/test/CodeGen/aarch64-neon-intrinsics.c
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_34/test/CodeGen/aarch64-neon-intrinsics.c?rev=196678&r1=196677&r2=196678&view=diff
==============================================================================
--- cfe/branches/release_34/test/CodeGen/aarch64-neon-intrinsics.c (original)
+++ cfe/branches/release_34/test/CodeGen/aarch64-neon-intrinsics.c Sat Dec 7 18:02:12 2013
@@ -11369,3 +11369,93 @@ uint64_t test_vaddvq_u64(uint64x2_t a) {
return vaddvq_u64(a);
// CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
}
+
+float64x1_t test_vadd_f64(float64x1_t a, float64x1_t b) {
+ // CHECK-LABEL: test_vadd_f64
+ return vadd_f64(a, b);
+ // CHECK: fadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vmul_f64(float64x1_t a, float64x1_t b) {
+ // CHECK-LABEL: test_vmul_f64
+ return vmul_f64(a, b);
+ // CHECK: fmul d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vdiv_f64(float64x1_t a, float64x1_t b) {
+ // CHECK-LABEL: test_vdiv_f64
+ return vdiv_f64(a, b);
+ // CHECK: fdiv d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vmla_f64(float64x1_t a, float64x1_t b, float64x1_t c) {
+ // CHECK-LABEL: test_vmla_f64
+ return vmla_f64(a, b, c);
+ // CHECK: fmadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vmls_f64(float64x1_t a, float64x1_t b, float64x1_t c) {
+ // CHECK-LABEL: test_vmls_f64
+ return vmls_f64(a, b, c);
+ // CHECK: fmsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vfma_f64(float64x1_t a, float64x1_t b, float64x1_t c) {
+ // CHECK-LABEL: test_vfma_f64
+ return vfma_f64(a, b, c);
+ // CHECK: fmadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vfms_f64(float64x1_t a, float64x1_t b, float64x1_t c) {
+ // CHECK-LABEL: test_vfms_f64
+ return vfms_f64(a, b, c);
+ // CHECK: fmsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vsub_f64(float64x1_t a, float64x1_t b) {
+ // CHECK-LABEL: test_vsub_f64
+ return vsub_f64(a, b);
+ // CHECK: fsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vabd_f64(float64x1_t a, float64x1_t b) {
+ // CHECK-LABEL: test_vabd_f64
+ return vabd_f64(a, b);
+ // CHECK: fabd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vmax_f64(float64x1_t a, float64x1_t b) {
+// CHECK-LABEL: test_vmax_f64
+ return vmax_f64(a, b);
+// CHECK: fmax d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vmin_f64(float64x1_t a, float64x1_t b) {
+// CHECK-LABEL: test_vmin_f64
+ return vmin_f64(a, b);
+// CHECK: fmin d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vmaxnm_f64(float64x1_t a, float64x1_t b) {
+// CHECK-LABEL: test_vmaxnm_f64
+ return vmaxnm_f64(a, b);
+// CHECK: fmaxnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vminnm_f64(float64x1_t a, float64x1_t b) {
+// CHECK-LABEL: test_vminnm_f64
+ return vminnm_f64(a, b);
+// CHECK: fminnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vabs_f64(float64x1_t a) {
+ // CHECK-LABEL: test_vabs_f64
+ return vabs_f64(a);
+ // CHECK: fabs d{{[0-9]+}}, d{{[0-9]+}}
+}
+
+float64x1_t test_vneg_f64(float64x1_t a) {
+ // CHECK-LABEL: test_vneg_f64
+ return vneg_f64(a);
+ // CHECK: fneg d{{[0-9]+}}, d{{[0-9]+}}
+}
More information about the llvm-branch-commits
mailing list