[llvm-branch-commits] [llvm-branch] r164533 - in /llvm/branches/R600: lib/Target/AMDGPU/AMDGPUInstructions.td lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp lib/Target/AMDGPU/R600Instructions.td test/CodeGen/R600/load.i8.ll

[Tom Stellard]

Author: tstellar
Date: Mon Sep 24 10:52:43 2012
New Revision: 164533

URL: http://llvm.org/viewvc/llvm-project?rev=164533&view=rev
Log:
R600: Add support for i8 reads on R600

Added:
    llvm/branches/R600/test/CodeGen/R600/load.i8.ll
Modified:
    llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td
    llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
    llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td

Modified: llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=164533&r1=164532&r2=164533&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td Mon Sep 24 10:52:43 2012
@@ -74,6 +74,14 @@
                      case ISD::SETLE: return true;}}}]
 >;
 
+//===----------------------------------------------------------------------===//
+// Load/Store Pattern Fragments
+//===----------------------------------------------------------------------===//
+
+def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
+    return isGlobalLoad(dyn_cast<LoadSDNode>(N));
+}]>;
+
 class Constants {
 int TWO_PI = 0x40c90fdb;
 int PI = 0x40490fdb;

Modified: llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp?rev=164533&r1=164532&r2=164533&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp Mon Sep 24 10:52:43 2012
@@ -165,6 +165,7 @@
       }
     case AMDGPU::VTX_READ_PARAM_i32_eg:
     case AMDGPU::VTX_READ_PARAM_f32_eg:
+    case AMDGPU::VTX_READ_GLOBAL_i8_eg:
     case AMDGPU::VTX_READ_GLOBAL_i32_eg:
     case AMDGPU::VTX_READ_GLOBAL_f32_eg:
     case AMDGPU::VTX_READ_GLOBAL_v4i32_eg:

Modified: llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td?rev=164533&r1=164532&r2=164533&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td Mon Sep 24 10:52:43 2012
@@ -1069,6 +1069,17 @@
   // Inst{127-96} = 0;
 }
 
+class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
+    : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
+
+  let MEGA_FETCH_COUNT = 1;
+  let DST_SEL_X = 0;
+  let DST_SEL_Y = 7;   // Masked
+  let DST_SEL_Z = 7;   // Masked
+  let DST_SEL_W = 7;   // Masked
+  let DATA_FORMAT = 1; // FMT_8
+}
+
 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
     : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
 
@@ -1121,6 +1132,11 @@
 // VTX Read from global memory space
 //===----------------------------------------------------------------------===//
 
+// 8-bit reads
+def VTX_READ_GLOBAL_i8_eg : VTX_READ_8_eg <1,
+  [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
+>;
+
 // 32-bit reads
 
 class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1,

Added: llvm/branches/R600/test/CodeGen/R600/load.i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/load.i8.ll?rev=164533&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/load.i8.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/load.i8.ll Mon Sep 24 10:52:43 2012
@@ -0,0 +1,10 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;CHECK: VTX_READ_eg T{{[0-9]+\.X, T[0-9]+\.X}}
+
+define void @test(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
+  %1 = load i8 addrspace(1)* %in
+  %2 = zext i8 %1 to i32
+  store i32 %2, i32 addrspace(1)* %out
+  ret void
+}