[llvm-branch-commits] [llvm-branch] r164532 - in /llvm/branches/R600: lib/Target/AMDGPU/AMDGPUISelLowering.cpp lib/Target/AMDGPU/AMDGPUInstrInfo.td lib/Target/AMDGPU/AMDGPUInstructions.td test/CodeGen/R600/llvm.AMDGPU.pow.ll test/CodeGen/R600/llvm.pow.ll

[Tom Stellard]

Author: tstellar
Date: Mon Sep 24 10:52:40 2012
New Revision: 164532

URL: http://llvm.org/viewvc/llvm-project?rev=164532&view=rev
Log:
R600: Replace AMDGPU pow intrinsic with the llvm version

Added:
    llvm/branches/R600/test/CodeGen/R600/llvm.pow.ll
      - copied, changed from r164531, llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll
Removed:
    llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll
Modified:
    llvm/branches/R600/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstrInfo.td
    llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td

Modified: llvm/branches/R600/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=164532&r1=164531&r2=164532&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Mon Sep 24 10:52:40 2012
@@ -34,6 +34,7 @@
   // for them.
   setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
   setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
+  setOperationAction(ISD::FPOW,   MVT::f32, Legal);
   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
 
   setOperationAction(ISD::UDIV, MVT::i32, Expand);

Modified: llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstrInfo.td?rev=164532&r1=164531&r2=164532&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstrInfo.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstrInfo.td Mon Sep 24 10:52:40 2012
@@ -67,3 +67,5 @@
 // out = (2^32 / a) + e
 // e is rounding error
 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
+
+def fpow : SDNode<"ISD::FPOW", SDTFPBinOp>;

Modified: llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=164532&r1=164531&r2=164532&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td Mon Sep 24 10:52:40 2012
@@ -128,7 +128,7 @@
 
 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
                   RegisterClass rc> : Pat <
-  (int_AMDGPU_pow rc:$src0, rc:$src1),
+  (fpow rc:$src0, rc:$src1),
   (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
 >;
 

Removed: llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll?rev=164531&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll (original)
+++ llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll (removed)
@@ -1,19 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: LOG_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK-NEXT: EXP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test() {
-   %r0 = call float @llvm.R600.load.input(i32 0)
-   %r1 = call float @llvm.R600.load.input(i32 1)
-   %r2 = call float @llvm.AMDGPU.pow( float %r0, float %r1)
-   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
-   ret void
-}
-
-declare float @llvm.R600.load.input(i32) readnone
-
-declare void @llvm.AMDGPU.store.output(float, i32)
-
-declare float @llvm.AMDGPU.pow(float ,float ) readnone

Copied: llvm/branches/R600/test/CodeGen/R600/llvm.pow.ll (from r164531, llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/llvm.pow.ll?p2=llvm/branches/R600/test/CodeGen/R600/llvm.pow.ll&p1=llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll&r1=164531&r2=164532&rev=164532&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/llvm.AMDGPU.pow.ll (original)
+++ llvm/branches/R600/test/CodeGen/R600/llvm.pow.ll Mon Sep 24 10:52:40 2012
@@ -7,7 +7,7 @@
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)
    %r1 = call float @llvm.R600.load.input(i32 1)
-   %r2 = call float @llvm.AMDGPU.pow( float %r0, float %r1)
+   %r2 = call float @llvm.pow.f32( float %r0, float %r1)
    call void @llvm.AMDGPU.store.output(float %r2, i32 0)
    ret void
 }
@@ -16,4 +16,4 @@
 
 declare void @llvm.AMDGPU.store.output(float, i32)
 
-declare float @llvm.AMDGPU.pow(float ,float ) readnone
+declare float @llvm.pow.f32(float ,float ) readonly