[llvm-branch-commits] [llvm-branch] r164512 - /llvm/branches/R600/lib/Target/Mips/MipsDSPInstrFormats.td

[Tom Stellard]

Author: tstellar
Date: Mon Sep 24 10:52:01 2012
New Revision: 164512

URL: http://llvm.org/viewvc/llvm-project?rev=164512&view=rev
Log:
MIPS DSP: Add predicates and instruction template.

Added:
    llvm/branches/R600/lib/Target/Mips/MipsDSPInstrFormats.td

Added: llvm/branches/R600/lib/Target/Mips/MipsDSPInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Mips/MipsDSPInstrFormats.td?rev=164512&view=auto
==============================================================================
--- llvm/branches/R600/lib/Target/Mips/MipsDSPInstrFormats.td (added)
+++ llvm/branches/R600/lib/Target/Mips/MipsDSPInstrFormats.td Mon Sep 24 10:52:01 2012
@@ -0,0 +1,25 @@
+//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+def HasDSP : Predicate<"Subtarget.hasDSP()">,
+             AssemblerPredicate<"FeatureDSP">;
+def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
+               AssemblerPredicate<"FeatureDSPR2">;
+
+// Fields.
+class Field6<bits<6> val> {
+  bits<6> V = val;
+}
+
+def SPECIAL3_OPCODE : Field6<0b011111>;
+def REGIMM_OPCODE : Field6<0b000001>;
+
+class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
+  let Predicates = [HasDSP];
+}